Data Sheet
FEATURES
Quad, 16-Bit, 125 MSPS, Serial LVDS 1.8 V Analog-to-Digital Converter AD9653
FUNCTIONAL BLOCK DIAGR...
Data Sheet
FEATURES
Quad, 16-Bit, 125 MSPS, Serial LVDS 1.8 V Analog-to-Digital Converter AD9653
FUNCTIONAL BLOCK DIAGRAM
AVDD PDWN 16 DRVDD SERIAL LVDS SERIAL LVDS SERIAL LVDS SERIAL LVDS REF SELECT AGND VIN+C VIN–C VIN+D VIN–D PIPELINE ADC 16 DIGITAL SERIALIZER 1V D0+A D0–A D1+A D1–A D0+B D0–B D1+B D1–B FCO+ FCO– D0+C D0–C D1+C D1–C D0+D D0–D D1+D D1–D DCO+ DCO– VIN+A VIN–A VIN+B VIN–B RBIAS VREF SENSE DIGITAL SERIALIZER DIGITAL SERIALIZER PIPELINE ADC PIPELINE ADC
SDIO/OLM
CSB
SCLK/DTP
SYNC
CLK+
CLK–
1.8 V supply operation Low power: 164 mW per channel at 125 MSPS SNR = 76.5 dBFS at 70 MHz (2.0 V p-p input span) SNR = 77.5 dBFS at 70 MHz (2.6 V p-p input span) SFDR = 90 dBc (to Nyquist, 2.0 V p-p input span) DNL = ±0.7 LSB; INL = ±3.5 LSB (2.0 V p-p input span) Serial LVDS (ANSI-644, default) and low power, reduced range option (similar to IEEE 1596.3) 650 MHz full power analog bandwidth 2 V p-p input
voltage range (supports up to 2.6 V p-p) Serial port control Full chip and individual channel power-down modes Flexible bit orientation Built-in and custom digital test pattern generation Multichip sync and clock divider Programmable output clock and data alignment Standby mode
16
AD9653
SERIAL LVDS SERIAL LVDS SERIAL LVDS SERIAL LVDS
PIPELINE ADC SERIAL PORT INTERFACE
16
DIGITAL SERIALIZER CLOCK MANAGEMENT
VCM
APPLICATIONS
Medical ultrasound and MRI High speed imaging Quadrature radio receivers Diversity radio receivers Test equipment
Figure 1.
GENERAL DESCR...