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AD9695 Datasheet

Part Number AD9695
Manufacturers Analog Devices
Logo Analog Devices
Description Dual Analog-to-Digital Converter
Datasheet AD9695 DatasheetAD9695 Datasheet (PDF)

Data Sheet 14-Bit, 1300 MSPS/625 MSPS, JESD204B, Dual Analog-to-Digital Converter AD9695 FEATURES JESD204B (Subclass 1) coded serial digital outputs Lane rates up to 16 Gbps 1.6 W total power at 1300 MSPS 800 mW per ADC channel SNR = 65.6 dBFS at 172 MHz (1.59 V p-p input range) SFDR = 78 dBFS at 172.3 MHz (1.59 V p-p input range) Noise density −153.9 dBFS/Hz (1.59 V p-p input range) −155.6 dBFS/Hz (2.04 V p-p input range) 0.95 V, 1.8 V, and 2.5 V supply operation No missing codes Internal ADC.

  AD9695   AD9695






Part Number AD9698
Manufacturers Analog Devices
Logo Analog Devices
Description Ultrafast TTL Comparators
Datasheet AD9695 DatasheetAD9698 Datasheet (PDF)

a FEATURES 4.5 ns Propagation Delay 200 ps Maximum Propagation Delay Dispersion Single +5 V or ؎ 5 V Supply Operation Complementary Matched TTL Outputs APPLICATIONS High Speed Line Receivers Peak Detectors Window Comparators High Speed Triggers Ultrafast Pulse Width Discriminators Ultrafast TTL Comparators AD9696/AD9698 Both devices allow the use of either a single +5 V supply or ± 5 V supplies. The choice of supplies determines the common mode input voltage range available: –2.2 V to +3.7 V fo.

  AD9695   AD9695







Part Number AD9697
Manufacturers Analog Devices
Logo Analog Devices
Description Analog-to-Digital Converter
Datasheet AD9695 DatasheetAD9697 Datasheet (PDF)

Data Sheet 14-Bit, 1300 MSPS, JESD204B, Analog-to-Digital Converter AD9697 FEATURES JESD204B (Subclass 1) coded serial digital outputs Lane rates up to 16 Gbps Total power dissipation: 1.00 W at 1300 MSPS SNR: 65.6 dBFS at 172.3 MHz (1.59 V p-p analog input full scale) SFDR: 78 dBFS at 172.3 MHz (1.59 V p-p analog input full scale) Noise density −153.9 dBFS/Hz (1.59 V p-p analog input full scale) −155.6 dBFS/Hz (2.04 V p-p analog input full scale) 0.95 V, 1.8 V, and 2.5 V supply operation No m.

  AD9695   AD9695







Part Number AD9696
Manufacturers Analog Devices
Logo Analog Devices
Description Ultrafast TTL Comparators
Datasheet AD9695 DatasheetAD9696 Datasheet (PDF)

a FEATURES 4.5 ns Propagation Delay 200 ps Maximum Propagation Delay Dispersion Single +5 V or ؎ 5 V Supply Operation Complementary Matched TTL Outputs APPLICATIONS High Speed Line Receivers Peak Detectors Window Comparators High Speed Triggers Ultrafast Pulse Width Discriminators Ultrafast TTL Comparators AD9696/AD9698 Both devices allow the use of either a single +5 V supply or ± 5 V supplies. The choice of supplies determines the common mode input voltage range available: –2.2 V to +3.7 V fo.

  AD9695   AD9695







Part Number AD9694-EP
Manufacturers Analog Devices
Logo Analog Devices
Description Quad Analog-to-Digital Converter
Datasheet AD9695 DatasheetAD9694-EP Datasheet (PDF)

Data Sheet AD9694-EP Enhanced Product FEATURES 14-Bit, 500 MSPS, JESD204B, Quad Analog-to-Digital Converter ► Flexible JESD204B lane configurations ► JESD204B (Subclass 1) coded serial digital outputs ► Lane rates up to 15 Gbps ► 1.66 W total power dissipation at 500 MSPS ► 415 mW per ADC channel ► SFDR = 82 dBFS at 305 MHz (1.80 V p-p input range) ► SNR = 66.8 dBFS at 305 MHz (1.80 V p-p input range) ► Noise density = −151.5 dBFS/Hz (1.80 V p-p input range) ► 0.975 V, 1.8 V, and 2.5 V dc sup.

  AD9695   AD9695







Dual Analog-to-Digital Converter

Data Sheet 14-Bit, 1300 MSPS/625 MSPS, JESD204B, Dual Analog-to-Digital Converter AD9695 FEATURES JESD204B (Subclass 1) coded serial digital outputs Lane rates up to 16 Gbps 1.6 W total power at 1300 MSPS 800 mW per ADC channel SNR = 65.6 dBFS at 172 MHz (1.59 V p-p input range) SFDR = 78 dBFS at 172.3 MHz (1.59 V p-p input range) Noise density −153.9 dBFS/Hz (1.59 V p-p input range) −155.6 dBFS/Hz (2.04 V p-p input range) 0.95 V, 1.8 V, and 2.5 V supply operation No missing codes Internal ADC voltage reference Flexible input range 1.36 V p-p to 2.04 V p-p (1.59 V p-p typical) 2 GHz usable analog input full power bandwidth >95 dB channel isolation/crosstalk Amplitude detect bits for efficient AGC implementation 2 integrated digital downconverters per ADC channel 48-bit NCO Programmable decimation rates Differential clock input SPI control Integer clock divide by 2 and divide by 4 Flexible JESD204B lane configurations On-chip dithering to improve small signal linerarity APPLICATI.


2019-06-19 : EEHZK1V101XP    EEHZK1V101XV    EEHZK1E470R    ERJPA3    ERJP06    ERJP08    ERJP14    MLG0603PPA    AD9695    EEHZK1E151XP   


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