ADC08B200Q

ADC08B200 www.ti.com SNAS388F – MARCH 2007 – REVISED APRIL 2013 ADC08B200 / ADC08B200Q 8-Bit, 200 MSPS A/D Converter with Capture Buffer Check for Samples: ADC08B200 FEATURES 1 2 Single-Ended Input Selectable Capture Buffer Size PLL for Clock Multiplication Reference Ladder Top and Bottom Accessible Linear Power Scaling with Sample Rate FPGA Training Pattern AEC-Q100 Grade 2 Qualified Power-Down Feature APPLICATIONS Laser Ranging RADAR Pulse Capturing KEY SPECIFICATIONS (PLL Bypassed) Resolution 8 Bits Maximum Sampling Frequency 200 MSPS (min) DNL ±0.4 LSB (typ) ENOB (fIN= 49 MHz) 7.2 bits (typ) THD (fIN= 49 MHz) −53 dBc (typ) Power Consumption – Operating (50 MHz) Input 2 mW / Msps (typ) – Power Down 2.15 mW (typ) DESCRIPTION The ADC08B200 is a high speed analog-to-digital converter (ADC) with an integrated capture buffer. The 8-bit, 200 MSPS A/D core is based upon the proven ADC08200 with integrated track-and-hold and is optimized for low power consumption. This device contains a selectable size capture buffer of up to 1,024 bytes that allows fast capture of an input signal with a slower readout rate. An on-chip clock PLL circuit provides the option of on-chip clock rate multiplication to provide the high speed sampling clock. The ADC08B200 is resistant to latch-up and the outputs are short-circuit proof. The top and bottom of the ADC08B200's reference ladder are available for connections, enabling a wide range of input possibilities. T...