ADC12DJ3200

Product Folder Order Now Technical Documents Tools & Software Support & Community ADC12DJ3200 SLVSD97A – JUNE 2017 – REVISED APRIL 2020 ADC12DJ3200 6.4-GSPS Single-Channel or 3.2-GSPS Dual-Channel, 12-bit, RF-Sampling Analog-to-Digital Converter (ADC) 1 Features 1 ADC core: – 12-bit resolution – Up to 6.4 GSPS in single-channel mode – Up to 3.2 GSPS in dual-channel mode Performance specifications: – Noise floor (no signal, VFS = 1.0 VPP-DIFF): – Dual-channel mode: –151.8 dBFS/Hz – Single-channel mode: –154.6 dBFS/Hz – HD2, HD3: –65 dBc up to 3 GHz Buffered analog inputs with VCMI of 0 V: – Analog input bandwidth (–3 dB): 8.0 GHz – Usable input frequency range: >10 GHz – Full-scale input voltage (VFS, default): 0.8 VPP – Analog input common-mode (VICM): 0 V Noiseless aperture delay (TAD) adjustment: – Precise sampling control: 19-fs step – Simplifies synchronization and interleaving – Temperature and voltage invariant delays Easy-to-use synchronization features: – Automatic SYSREF timing calibration – Timestamp for sample marking JESD204B serial data interface: – Supports subclass 0 and 1 – Maximum lane rate: 12.8 Gbps – Up to 16 lanes allows reduced lane rate Digital down-converters in dual-channel mode: – Real output: DDC bypass or 2x decimation – Complex output: 4x, 8x, or 16x decimation – Four independent 32-Bit NCOs per DDC Power consumption: 3 W Power supplies: 1.1 V, 1.9 V ADC12DJ3200 Measured Input Bandwidth 3 Normalized Gain Response (dB) 0 ...