ADC12DL065

ADC12DL065 www.ti.com SNAS249D – MARCH 2005 – REVISED APRIL 2013 ADC12DL065 Dual 12-Bit, 65 MSPS, 3.3V, 360mW A/D Converter Check for Samples: ADC12DL065 FEATURES 1 2 Single +3.3V Supply operation Internal Sample-and-Hold Internal Reference Outputs 2.4V to 3.6V Compatible Power Down Mode Duty Cycle Stabilizer Multiplexed Output Mode APPLICATIONS Ultrasound and Imaging Instrumentation Communications Receivers Sonar/Radar xDSL Cable Modems DSP Front Ends KEY SPECIFICATIONS Resolution: 12 Bits DNL: ±0.4 LSB (typ) SNR (fIN = 10 MHz): 69 dB (typ) SFDR (fIN = 10 MHz): 86 dB (typ) Data Latency: 7 Clock Cycles Power Consumption – Operating: 360 mW (typ) – Power Down Mode: 36 mW (typ) DESCRIPTION The ADC12DL065 is a dual, low power monolithic CMOS analog-to-digital converter capable of converting analog input signals into 12-bit digital words at 65 Megasamples per second (MSPS). This converter uses a differential, pipeline architecture with digital error correction and an on-chip sample-andhold circuit to minimize power consumption while providing excellent dynamic performance and a 250 MHz Full Power Bandwidth. Operating on a single +3.3V power supply, the ADC12DL065 achieves 11.0 effective bits at nyquist and consumes just 360 mW at 65 MSPS, including the reference current. The Power Down feature reduces power consumption to 36 mW. The differential inputs provide a full scale differential input swing equal to 2 times VREF with the possibil...