ADC12J1600

Product Folder Order Now Technical Documents Tools & Software Support & Community ADC12J1600, ADC12J2700 SLAS969D – JANUARY 2014 – REVISED OCTOBER 2017 ADC12Jxx00 12-Bit 1.6- or 2.7-GSPS ADCs With Integrated DDC 1 Features 1 Excellent Noise and Linearity up to and beyond FIN = 3 GHz Configurable DDC Decimation Factors from 4 to 32 (Complex Baseband Out) Bypass Mode for Full Nyquist Output Bandwidth Usable Output Bandwidth of 540 MHz at 4x Decimation and 2700 MSPS Usable Output Bandwidth of 320 MHz at 4x Decimation and 1600 MSPS Usable Output Bandwidth of 67.5 MHz at 32x Decimation and 2700 MSPS Usable Output Bandwidth of 40 MHz at 32x Decimation and 1600 MSPS Low Pin-Count JESD204B Subclass 1 Interface Automatically Optimized Output Lane Count Embedded Low Latency Signal Range Indication Low Power Consumption Key Specifications: – Max Sampling Rate: 1600 or 2700 MSPS – Min Sampling Rate: 1000 MSPS – DDC Output Word Size: 15-Bit Complex (30 bits total) – Bypass Output Word Size: 12-Bit Offset Binary – Noise Floor: –147.3 dBFS/Hz (ADC12J2700) – Noise Floor: –145 dBFS/Hz (ADC12J1600) – IMD3: −64 dBc (FIN = 2140 MHz ± 30 MHz at −13 dBFS) – FPBW (–3 dB): 3.2 GHz – Peak NPR: 46 dB – Supply Voltages: 1.9 V and 1.2 V – Power Consumption – Bypass (2700 MSPS): 1.8 W – Bypass (1600 MSPS): 1.6 W – Power Down Mode: <50 mW 2 Applications Wireless Infrastructure RF-Sampling Software Defined Radio Wideband Microwave Backhaul Military Communications S...