ADC12J4000

Product Folder Order Now Technical Documents Tools & Software Support & Community ADC12J4000 SLAS989D – JANUARY 2014 – REVISED OCTOBER 2017 ADC12J4000 12-Bit, 4-GSPS ADC With Integrated DDC 1 Features 1 Excellent Noise and Linearity up to and beyond FIN = 3 GHz Configurable DDC Decimation Factors from 4 to 32 (Complex Baseband Out) Usable Output Bandwidth of 800 MHz at 4x Decimation and 4000 MSPS Usable Output Bandwidth of 100 MHz at 32x Decimation and 4000 MSPS Bypass Mode for Full Nyquist Output Bandwidth Low Pin-Count JESD204B Subclass 1 Interface Automatically Optimized Output Lane Count Embedded Low Latency Signal Range Indication Low Power Consumption Key Specifications: – Max Sampling Rate: 4000 MSPS – Min Sampling Rate: 1000 MSPS – DDC Output Word Size: 15-Bit Complex (30 bits total) – Bypass Output Word Size: 12-Bit Offset Binary – Noise Floor: −149 dBFS/Hz or −150.8 dBm/Hz – IMD3: −64 dBc (FIN = 2140 MHz ± 30 MHz at −13 dBFS) – FPBW (–3 dB): 3.2 GHz – Peak NPR: 46 dB – Supply Voltages: 1.9 V and 1.2 V – Power Consumption – Bypass (4000 MSPS): 2 W – Decimate by 10 (4000 MSPS): 2 W – Power Down Mode: <50 mW 2 Applications Wireless Infrastructure RF-Sampling Software Defined Radio Wideband Microwave Backhaul Military Communications SIGINT RADAR and LIDAR DOCSIS / Cable Infrastructure Test and Measurement 3 Description The ADC12J4000 device is a wideband sampling and digital tuning device. Texas Instruments' giga-sample analo...