ADC12QS065

PRELIMINARY www.DataSheet4U.com November 2005 ADC12QS065 Quad 12-Bit 65 MSPS A/D Converter with LVDS Serialized Outputs ADC12QS065 Quad 12-Bit 65 MSPS A/D Converter with LVDS Serialized Outputs General Description This is Preliminary Information for a product currently in development. ALL specifications are design targets and are subject to change. The ADC12QS065 is a low power, high performance CMOS 4-channel analog-to-digital converter with LVDS serialized outputs. The ADC12QS065 digitizes signals to 12 bits resolution at sampling rates up to 65 MSPS while consuming a typical 200 mW/ADC from a single 3.0V supply. Sampled data is transformed into high speed serial LVDS output data streams. Clock and frame LVDS pairs aid in data capture. The ADC12QS065’s six differential pairs transmit data over backplanes or cable and also make PCB design easier. In addition, the reduced cable, PCB trace count, and connector size tremendously reduce cost. No missing codes performance is guaranteed over the full operating temperature range. The pipeline ADC architecture achieves > 11 Effective Bits over the entire Nyquist band at 65 MSPS. The ADC12QS065 output pins can be put into a high impedance state. The serializer PLL can lock to frequencies between 20 MHz and 65 MHz. When not converting, power consumption can be reduced by pulling the PD (Power Down) pin high, placing the converter into a low power state where it typically consumes less than 3 mW total, and from which recovery is less...