ADP7112

Data Sheet FEATURES Low noise: 11 μV rms independent of fixed output voltage PSRR of 88 dB at 10 kHz, 68 dB at 100 kHz, 50 dB at 1 MHz, VOUT = 5 V, VIN = 7 V Input voltage range: 2.7 V to 20 V Maximum output current: 200 mA Initial accuracy: ±0.8% Accuracy over line, load, and temperature ±1.8%, TJ = −40°C to +125°C Low dropout voltage: 200 mV (typical) at a 200 mA load, VOUT = 5 V User-programmable soft start Low quiescent current, IGND = 50 μA (typical) with no load Low shutdown current 1.8 μA at VIN = 5 V 3.0 μA at VIN = 20 V Stable with a small 2.2 μF ceramic output capacitor Fixed output voltage options: 1.8 V, 2.5 V, 3.3 V, and 5.0 V 15 standard voltages between 1.2 V and 5.0 V are available Adjustable output from 1.2 V to VIN – VDO, output can be adjusted above initial set point Precision enable 1 mm × 1.2 mm, 6-ball WLCSP APPLICATIONS Regulation to noise sensitive applications ADC and DAC circuits, precision amplifiers, power for VCO VTUNE control Communications and infrastructure Medical and healthcare Industrial and instrumentation GENERAL DESCRIPTION The ADP7112 is a CMOS, low dropout (LDO) linear regulator that operates from 2.7 V to 20 V and provides up to 200 mA of output current. This high input voltage LDO is ideal for the regulation of high performance analog and mixed-signal circuits operating from 19 V down to 1.2 V rails. Using an advanced proprietary architecture, the device provides high power supply rejection, low noise, and achieves excellent line and ...