ADS42JB46

Product Folder Sample & Buy Technical Documents Tools & Software Support & Community ADS42JB46 SBAS621B – JULY 2013 – REVISED SEPTEMBER 2015 ADS42JB46 Dual-Channel, 14-Bit, 160-MSPS Analog-to-Digital Converter 1 Features 1 Dual-Channel ADCs 14-Bit Resolution Maximum Clock Rate: 160 MSPS JESD204B Serial Interface – Subclass 0, 1, 2 Compliant – Up to 3.125 Gbps – Two- and Four-Lane Support Analog Input Buffer with High-Impedance Input Flexible Input Clock Buffer: Divide-by-1, -2, and -4 Differential Full-Scale Input: 2 VPP and 2.5 VPP (Register Programmable) Package: 9-mm × 9-mm QFN-64 Power Dissipation: 679 mW/Ch Aperture Jitter: 85 fS rms Internal Dither Channel Isolation: 100 dB Performance: – fIN = 170 MHz at 2 VPP, –1 dBFS – SNR: 72.9 dBFS – SFDR: 90 dBc for HD2, HD3 – SFDR: 100 dBc for Non HD2, HD3 – fIN = 170 MHz at 2.5 VPP, –1 dBFS – SNR: 74.2 dBFS – SFDR: 84 dBc for HD2, HD3 and 95 dBc for Non HD2, HD3 Simplified Schematic INAP, INAM CLKINP, CLKINM SYSREFP, SYSREFM INBP, INBM VCM Device 14-, 16-Bit ADC Digital Block Gain Test Modes JESD204B Digital Divide by 1, 2, 4 PLL x10, x20 Delay Common Mode 14-, 16-Bit ADC Digital Block Gain Test Modes JESD204B Digital Device Configuration OVRA DA0P, DA0M DA1P, DA1M SYNC~P, SYNC~M DB0P, DB0M DB1P, DB1M OVRB 2 Applications Communication and Cable Infrastructure Multi-Carrier, Multimode Cellular Receivers Radar and Smart Antenna Arrays Broadband Wireless Test and Measurement S...