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ADS61JB23 Datasheet

Part Number ADS61JB23
Manufacturers Texas Instruments
Logo Texas Instruments
Description Analog-to-Digital Converters
Datasheet ADS61JB23 DatasheetADS61JB23 Datasheet (PDF)

ADS61JB23 www.ti.com SLOS755 – DECEMBER 2012 12-Bit Input-Buffered 80 MSPS ADC with JESD204A Output Interface Check for Samples: ADS61JB23 FEATURES 1 • Output Interface: – Single-Lane and Dual-Lane Interfaces – Maximum Data Rate of 1.6 Gbps – Meets JESD204A Specification – CML Outputs with Current Programmable from 2 mA – 32 mA • Power Dissipation: – 440 mW at 80 MSPS in Single Lane Mode – Power Scales Down with Clock Rate • Input Interface: Buffered Analog Inputs • 71.7 dBFS SNR at 70 MHz I.

  ADS61JB23   ADS61JB23






Analog-to-Digital Converters

ADS61JB23 www.ti.com SLOS755 – DECEMBER 2012 12-Bit Input-Buffered 80 MSPS ADC with JESD204A Output Interface Check for Samples: ADS61JB23 FEATURES 1 • Output Interface: – Single-Lane and Dual-Lane Interfaces – Maximum Data Rate of 1.6 Gbps – Meets JESD204A Specification – CML Outputs with Current Programmable from 2 mA – 32 mA • Power Dissipation: – 440 mW at 80 MSPS in Single Lane Mode – Power Scales Down with Clock Rate • Input Interface: Buffered Analog Inputs • 71.7 dBFS SNR at 70 MHz IF • Analog Input FSR: 2 Vpp • External and Internal (trimmed) Reference Support • 1.8V Supply (Analog and digital), 3.3 V Supply for Input Buffer • Programmable Digital Gain: 0dB – 6dB • Straight Offset Binary or Twos Complement Output • Package: – 6 mm x 6 mm QFN-40 APPLICATIONS • Wireless Base-station Infrastructure • Test and Measurement Instrumentation DESCRIPTION The ADS61JB23 is a high-performance, low-power, single channel analog-to-digital converter with an integrated JESD204A output interface. Available in a 6 mm x 6 mm QFN package, with both single-lane and dual-lane output modes, the ADS61JB23 offers an unprecedented level of compactness. The output interface is compatible to the JESD204A standard, with an additional mode (as per IEEE Std 802.3-2002 part3, Clause 36.2.4.12) to interface seamlessly to the TI TLK family of SERDES transceivers. Equally impressive is the inclusion of an onchip analog input buffer, providing isolation between the sample/hold switches and higher.


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