ADS62P22

ADS62P24, ADS62P25 ADS62P22, ADS62P23 www.ti.com SLAS576C – OCTOBER 2007 – REVISED OCTOBER 2011 DUAL CHANNEL, 12-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS Check for Samples: ADS62P24, ADS62P25, ADS62P22, ADS62P23 FEATURES 1 Maximum Sample Rate: 125 MSPS 12-Bit Resolution with No Missing Codes 95 dB Crosstalk Parallel CMOS and DDR LVDS Output Options 3.5 dB Coarse Gain and Programmable Fine Gain up to 6 dB for SNR/SFDR Trade-Off Digital Processing Block with: – Offset Correction – Fine Gain Correction, in Steps of 0.05 dB – Decimation by 2/4/8 – Built-in and Custom Programmable 24-Tap Low-/High-/Band-Pass Filters Supports Sine, LVPECL, LVDS, and LVCMOS Clocks and Amplitude Down to 400 mVPP Clock Duty Cycle Stabilizer Internal Reference; Supports External Reference also 64-QFN Package (9mm × 9mm) Pin Compatible 14-Bit Family (ADS62P4X) APPLICATIONS Wireless Communications Infrastructure Software Defined Radio Power Amplifier Linearization 802.16d/e Test and Measurement Instrumentation High Definition Video Medical Imaging Radar Systems DESCRIPTION ADS62P2X is a dual channel 12-bit A/D converter family with maximum sample rates up to 125 MSPS. It combines high performance and low power consumption in a compact 64 QFN package. Using an internal sample and hold and low jitter clock buffer, the ADC supports high SNR and high SFDR at high input frequencies. It has coarse and fine gain options that can be used to improve SFDR ...