ADS62P28

www.ti.com ADS62P49 / ADS62P29 ADS62P48 / ADS62P28 SLAS635B – APRIL 2009 – REVISED JANUARY 2011 Dual Channel 14-/12-Bit, 250-/210-MSPS ADC With DDR LVDS and Parallel CMOS Outputs Check for Samples: ADS62P49 / ADS62P29, ADS62P48 / ADS62P28 FEATURES 1 Maximum Sample Rate: 250 MSPS 14-Bit Resolution – ADS62P49/ADS62P48 12-Bit Resolution – ADS62P29/ADS62P28 Total Power: 1.25 W at 250 MSPS Double Data Rate (DDR) LVDS and Parallel CMOS Output Options Programmable Gain up to 6dB for SNR/SFDR Trade-Off DC Offset Correction 90dB Cross-Talk Supports Input Clock Amplitude Down to 400 mVPP Differential Internal and External Reference Support 64-QFN Package (9 mm × 9 mm) ADS62Pxx High Speed Family 250 MSPS 210 MSPS 200 MSPS 14-Bit Family ADS62P49 ADS62P48 12-Bit Family ADS62P29 ADS62P28 11-Bit Family ADS62C17 DESCRIPTION The ADS62Px9/x8 is a family of dual channel 14-bit and 12-bit A/D converters with sampling rates up to 250 MSPS. It combines high dynamic performance and low power consumption in a compact 64 QFN package. This makes it well-suited for multi-carrier, wide band-width communications applications. The ADS62Px9/x8 has gain options that can be used to improve SFDR performance at lower full-scale input ranges. It includes a dc offset correction loop that can be used to cancel the ADC offset. Both DDR LVDS (Double Data Rate) and parallel CMOS digital output interfaces are available. It includes internal references while the traditional reference...