Translator Guide. AN1672D Datasheet

AN1672D Datasheet PDF

Part Number



The ECL Translator Guide


ON Semiconductor

Total Page 10 Pages
Download AN1672D Datasheet

The ECL Translator Guide
Prepared by: Paul Shockman
ON Semiconductor
This application note is intended to provide the basic
device selection and connection information to enable signal
translation interface between ON Semiconductor’s ECL
logic operating in various supply modes This document also
provides information regarding translation between our
ECL devices and TTL (5 V), CMOS (5 V), or
LVTTL/LVCMOS (3.3 V) devices. For translation interface
with LVDS, see AN1568.
Translation to and from ECL technology is discussed in
three section divisions:
Section 1. Translation between differently supplied
ECL drivers and receivers
Section 2. Translation from different ECL operating
mode drivers to non ECL receivers
Section 3. Translation from non ECL drivers to
different ECL operating mode receivers
Proper translation occurs when the driver’s output logic
levels are within the spec limits of the receiver and are
recognized. Specific device data sheets should be consulted
for exact specifications and parameter limits.
IBIS and SPICE models may be found at for most devices. General ECL
information, also online, may be consulted such as
AND8020, AND8066, and AND8072.
General Background
TTL and CMOS drivers generally source current (to the
receiver) in the HIGH state and sink current (from the
receiver) in the LOW state. In contrast, ECL drivers source
current in both HIGH and LOW states (to the receiver).
Receiver inputs do not require any “termination” although
any driver may or may not require termination
considerations. The driver termination considerations may
be located physically near or internal to a receiver.
TTL and CMOS devices will usually be operated across
a single positive power supply (VCC or VDD) and ground.
ECL devices may operate similarly across a single Positive
supply and VEE (Ground) as Positive ECL (PECL) or Low
Voltage Positive ECL (LVPECL). Or traditionally, ECL
devices may span across Ground and a single negative
power supply, VEE, as Negative ECL (NECL) or Low
Voltage Negative ECL (LVNECL). Any device may be
operated with all pins offset by a fixed voltage, but interface
with standard levels may require a translation device. A pure
ECL device might be operated in NECL, PECL, or LVPECL
mode by simply shifting all voltage levels. Of course, a
translator dedicated to a specific technology will expect only
fixed voltages and can’t usually operate in different, or
shifted voltage modes.
© Semiconductor Components Industries, LLC, 2004
November, 2004 − Rev. 9
Publication Order Number:

Different ECL operating supply modes are generally
considered to be as presented below in Table 1.
Table 1. ECL Operating Supply Modes
VCC = 5.0, VEE = 0.0
VCC = 3.3, VEE = 0.0
VCC = 2.5, VEE = 0.0
VCC = 0.0, VEE = −2.5
VCC = 0.0, VEE = −3.3
VCC = 0.0, VEE = −5.0
Some devices may span one or more operating modes and
each mode will allow supply tolerances. ECL signal levels
(VOL, VOH, VIL, and VIH) are referenced from the VCC pin
or positive rail. Therefore, when ECL devices are operated
from different negative power supplies, no translation is
required for interconnects. When operated in a single ended
configuration, the critical Input parameters are VIL and VIH
limits (VIHCMR and Vpp are ignored). When operation
differentially, critical limit Input parameters are VIHCMR
and Vpp (VIL and VIH are ignored). See AND8066 for
interconnect details. All supply pins, VCC, LVCC, and
GND, must be connected for proper operation. A 0.1 mF to
0.01 mF decoupling cap is recommended from VCC to GND.
VCC ripple should be minimized and may require additional
filter networks.
Standard non ECL operating modes are generally
considered (with certain supply tolerances) to be as presented
below in Table 2.
Table 2. Non ECL Operating Supply Modes
VCC = 5.0, VEE = 0.0
VCC = 3.3, VEE = 0.0
VCC = 2.5, VEE = 0.0
Most translation interface between technologies will
require a separate, dedicated translator IC device, but some
newer ECL devices offer a translation feature integrated into
certain mode control pins. Several of the GigaComm
devices offer a programmable mode pins for selecting the
control pins translation levels. MC10EP195 offers Delay
Select pins with user programmable TTL, CMOS, or ECL
threshold levels.
An alternative translation technique, cap coupling, is
discussed in Application Note AND8020, Section 5. Cap
coupling may accommodate level shifting when the signal’s
“edge density” is sufficient. Otherwise, coding may be
required to increase ”edge density”. Certainly the risk of
erroneous levels, due to the coupling cap leakage, may not
be acceptable and system requirements may demand the
hard levels found with active device translation.

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