Bus Interface
ARINC 429 Bus Interface
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Product Summary
Intended Use
• • ARINC 429 Transmitter (Tx) ARINC 429 Recei...
Description
ARINC 429 Bus Interface
www.datasheet4u.com
Product Summary
Intended Use
ARINC 429 Transmitter (Tx) ARINC 429 Receiver (Rx)
Core Deliverables
Evaluation Version – Compiled RTL Simulation Model, Compliant with the Actel Libero® Integrated Design Environment (IDE) Structural VHDL and Verilog Netlists VHDL or Verilog Core Source Code Synthesis Scripts
Netlist Version – RTL version – –
Key Features
Supports ARINC Specification 429-16 Configurable up to 16 Rx and 16 Tx Channels Programmable FIFO Depth – – – – – Up to 512 Words Rx and Tx Channels independently Up to 64 Words Programmable Interrupt Generation
Verification Testbench – Verilog User Testbenches – – Libero IDE Compatible VHDL and Verilog
Configurable Label Memory Size Rx and Tx Channels independently Up to 256 Words
Development System
Complete ARINC 429 Rx/Tx Implementation – – Implemented in an APA600 Device Controlled Via an External Terminal Using Core8051 and RS232 Links
Internal, Wrap-Around Testing Software Compatible with Legacy Devices Selectable Clock Speed – – – 1, 10, 16, or 20 MHz 12.5 100 kbps Optional 50 kbps Provides Direct CPU Access to Memory Simple Interface to Core8051 EDAC Support with RTAX-S Family Supports Standard Line Drivers and Receivers Selectable Data Rate on Each Channel
Includes Line Driver and Receiver Components
Synthesis and Simulation Support
Directly Supported within the Actel Libero IDE Synthesis: – – – – – Synplicity® ExemplarTM...
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