AS7C33256PFD32A

December 2004 ® AS7C33256PFD32A AS7C33256PFD36A 3.3V 256K × 32/36 pipelined burst synchronous SRAM Features Organization: 262,144 words x 32 or 36 bits Fast clock speeds to 166 MHz Fast clock to data access: 3.5/4.0 ns Fast OE access time: 3.5/4.0 ns Fully synchronous register-to-register operation Dual-cycle deselect Asynchronous output enable control Available in100-pin TQFP Individual byte write and global write Multiple chip enables for easy expansion Linear or interleaved burst control Snooze mode for reduced power-standby Common data inputs and data outputs 3.3V core power supply 2.5V or 3.3V I/O operation with separate VDDQ www.DataSheet4U.com Logic block diagram LBO CLK ADV ADSC ADSP A[17:0] 18 Q0 Burst logic Q1 18 2 16 D Q CE Address register CLK D DQd Q Byte write registers CLK D DQ Q c Byte write registers CLK D DQb Q Byte write registers CLK D DQ Q a Byte write registers CLK D Enable CE register CLK Q CLK CE CLR 2 18 256K × 32/36 Memory array BWE GWE 36/32 36/32 BWd BWc BWb BWa CE0 CE1 CE2 4 OE Output registers CLK Input registers CLK ZZ Power down D Enable Q delay register CLK 36/32 DQ[a:d] OE Selection guide –166 Minimum cycle time Maximum clock frequency Maximum clock access time Maximum operating current Maximum standby current Maximum CMOS standby current (DC) 12/1/04, v.1.2 –133 7.5 133 4 425 100 30 Units ns MHz ns mA mA mA P. 1 of 20 6 166 3.5 475 130 30 Alliance Semiconductor Copyright ©Alliance S...