December 2004
®
AS7C332MFT18A
3.3V 2M × 18 Flow-through synchronous SRAM
Features
• • • • • • • Organization: 2,097152...
December 2004
®
AS7C332MFT18A
3.3V 2M × 18 Flow-through synchronous SRAM
Features
Organization: 2,097152 words × 18 bits Fast clock to data access: 7.5/8.5/10 ns Fast OE access time: 3.5/4.0 ns Fully synchronous flow-through operation Asynchronous output enable control Available in 100-pin TQFP package Individual byte write and global write Multiple chip enables for easy expansion 3.3V core power supply 2.5V or 3.3V I/O operation with separate VDDQ Linear or interleaved burst control Snooze mode for reduced power-standby Common data inputs and data outputs
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Logic block diagram
LBO
CLK ADV ADSC ADSP A[20:0] CLK CS CLR
Burst logic
Q
21
CS Address register CLK
D
21
19 21
2M x 18 Memory array 18 18
GWE BWb BWE BWa CE0 CE1 CE2
D DQb
Q
CLK D DQa Q
Byte Write registers
Byte Write
CLK D
registers
Enable register
2
OE
Q
CE CLK ZZ
Output registers
CLK
Input registers
CLK
Power down
D Enable Q
delay register
CLK OE
18
DQ[a,b]
Selection guide
Minimum cycle time Maximum clock access time Maximum operating current Maximum standby current Maximum
CMOS standby current (DC)
-75 8.5 7.5 325 140 90
-85 10 8.5 300 130 90
-10 12 10 275 130 90
Units ns ns mA mA mA
12/23/04, v 1.3
Alliance Semiconductor
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AS7C332MFT18A
®
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