EEPROM. AT17C128A Datasheet

AT17C128A Datasheet PDF

Part AT17C128A
Description FPGA Configuration EEPROM
Feature AT17C128A; Features • EE Programmable 65,536 x 1, 131,072 x 1 and 262,144 x 1 bit Serial Memories Designed to S.
Manufacture ATMEL Corporation
Datasheet
Download AT17C128A Datasheet




AT17C128A
Features
EE Programmable 65,536 x 1, 131,072 x 1 and 262,144 x 1 bit Serial Memories Designed
to Store Configuration Programs for Programmable Gate Arrays
Simple Interface to SRAM FPGAs Requires Only One User I/O Pin
Able to Configure with EPF6000 and EPF8000, Flex 10K FPGAs
Cascadable To Support Additional Configurations or Future Higher-Density Arrays
(17C128/256 only)
Low-Power CMOS EEPROM Process
Programmable Reset Polarity
Available in Industry-Standard Pin-Compatible PLCC Package
In-System Programmable via 2-Wire Bus
Emulation of 24CXX Serial EEPROMs
Available in 3.3V and 5V Versions
Description
The AT17C65/128/256A and AT17LV65/128/256A (AT17A Series) FPGA Configura-
tion EEPROMS (Configurator) provide an easy-to-use, cost-effective configuration
memory for Field Programmable Gate Arrays. The AT17A Series is packaged in the
popular 20-pin PLCC. The AT17A Series family uses a simple serial-access provides
to configure one or more FPGA devices. The AT17A Series organization supplies
enough memory to configure one or multiple smaller FPGAs. Using a special feature
of the AT17A Series, the user can select the polarity of the reset function by program-
ming a special EEPROM bit.
The AT17A Series is pin compatible with the industry standard configurator, and can
be programmed with industry standard programmers.
Pin Configurations
20-Pin PLCC
FPGA
Configuration
EEPROM
65K, 128K and 256K
AT17CxxxA
AT17LVxxxA
CLK (DCLK)
NC
NC
NC
RESET/OE (RESET/OE)
4
5
6
7
8
18 SER_EN
17 NC
16 NC
15 NC
14 NC
Rev. 0996A–07/98
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AT17C128A
Controlling The AT17A Series Serial EEPROMs
Most connections between the FPGA device and the serial
EEPROM are simple and self-explanatory.
• The DATA output of the AT17A Series drives DIN of the
FPGA devices.
• The master FPGA CCLK output drives the CLK input of
the AT17A Series.
• The CEO output of any AT17C/LV128/256A drives the
CE input of the next AT17C/LV65/128/256 in a cascade
chain of PROMs.
• SER_EN must be connected to VCC.
There are, however, two different ways to use the inputs
CE and OE, as shown in the AC Characteristics wave-
forms.
Condition 1
The simplest connection is to have the FPGA D/P output
drive both CE and RESET/OE in parallel (Figure 1). Due to
its simplicity, however, this method will fail if the FPGA
receives an external reset condition during the configura-
tion cycle. If a system reset is applied to the FPGA, it will
abort the original configuration and then reset itself for a
new configuration, as intended. Of course, the AT17A
Series does not see the external reset signal and will not
reset its internal address counters and, consequently, will
remain out of sync with the FPGA for the remainder of the
configuration cycle.
Condition 2
The FPGA D/P output drives only the CE input of the
AT17A Series, while its OE input is driven by the inversion
of the input to the FPGA RESET input pin. This connection
works under all normal circumstances, even when the user
aborts a configuration before D/P has gone high. A high
level on the RESET/OE input to the AT17C/LVxxxA – dur-
ing FPGA reset – clears the Configurator's internal address
pointer, so that the reconfiguration starts at the beginning.
The AT17A Series does not require an inverter since the
RESET polarity is programmable.
Block Diagram
2 AT17A Series



AT17C128A
AT17A Series
Pin Configurations
PLCC/S
OIC
DIP
Pin Pin Name
2 1 DATA
4 2 CLK
8 3 RESET/OE
9 4 CE
10 5 GND
12 6 CEO
A2
18 7 SER_EN
20 8 VCC
I/O Description
I/O Three-state DATA output for reading. Input/Output pin for programming.
I Clock input. Used to increment the internal address and bit counter for reading and
programming.
RESET/Output Enable input (when SER_EN is High). A low level on both the CE and
RESET/OE inputs enables the data output driver. A high level on RESET/OE resets both
the address and bit counters. A logic polarity of this input is programmable as either
RESET/OE or RESET/OE. This document describes the pin as RESET/OE.
I Chip Enable input. Used for device selection. A low level on both CE and OE enables the
data output driver. A high level on CE disables both the address and bit counters and
forces te device into a low-power mode. Note this pin will not enable/disable the device in
2-wire serial mode (ie; when SER_EN is low).
Ground pin
O Chip Enable Out output. This signal is asserted low on the clock cycle following the last
bit read from the memory. It will stay low as long as CE and OE are both low. It will then
follow CE until OE goes high. Thereafter, CEO will stay high until the entire PROM is
read again and senses the status of RESET polarity.
I Device selection input, A2. This is used to enable (or select) the device during
programming and when SER_EN is low (see Programming Guide for more details).
I Serial enable is normally high during FPGA loading operations. Bringing SER_EN low,
enables the 2-wire serial interface for programming.
+3.3V/+5V power supply pin.
Absolute Maximum Ratings*
Operating Temperature .................................. -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
Voltage on Any Pin
with Respect to Ground ............................. -0.1V to VCC + 0.5V
Supply Voltage (VCC) .......................................-0.5 V to + 7.0V
Maximum Soldering Temp. (10 sec. @ 1/16 in.) .............260°C
ESD (RZAP = 1.5K, CZAP = 100 pF)................................. 2000V
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
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