MPU. AT91RM9200 Datasheet

AT91RM9200 Datasheet PDF

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Total Page 30 Pages
Download AT91RM9200 Datasheet

Atmel | SMART ARM-based Embedded MPU
The Atmel® | SMART AT91RM9200 is a complete system-on-chip built around the
ARM920TARM® Thumb® processor. It incorporates a rich set of system and
application peripherals and standard interfaces in order to provide a single-chip
solution for a wide range of compute-intensive applications that require maximum
functionality at minimum power consumption at lowest cost.
The AT91RM9200 incorporates a high-speed on-chip SRAM workspace, and a
low-latency External Bus Interface (EBI) for seamless connection to whatever
configuration of off-chip memories and memory-mapped peripherals is required
by the application. The EBI incorporates controllers for synchronous DRAM
(SDRAM), Burst Flash and Static memories and features specific circuitry
facilitating the interface for NAND Flash/SmartMedia and CompactFlash.
The Advanced Interrupt Controller (AIC) enhances the interrupt handling
performance of the ARM920T processor by providing multiple vectored, prioritized
interrupt sources and reducing the time taken to transfer to an interrupt handler.
The Peripheral DMA Controller (PDC) provides DMA channels for all the serial
peripherals, enabling them to transfer data to or from on- and off-chip memories
without processor intervention. This reduces the processor overhead when
dealing with transfers of continuous data streams. The AT91RM9200 benefits
from a generation of PDC which includes dual pointers that significantly simplify
buffer chaining.
The set of Parallel I/O (PIO) controllers multiplex the peripheral input/output lines
with general-purpose data I/Os for maximum flexibility in device configuration. An
input change interrupt, open drain capability and programmable pull-up resistor is
included on each line.
The Power Management Controller (PMC) keeps system power consumption to a
minimum by selectively enabling/disabling the processor and various peripherals
under software control. It uses an enhanced clock generator to provide a selection
of clock signals including a slow clock (32 kHz) to optimize power consumption
and performance at all times.
The AT91RM9200 integrates a wide range of standard interfaces including USB
2.0 Full Speed Host and Device and Ethernet 10/100 Base-T Media Access
Controller (MAC), which provides connection to an extensive range of external
peripheral devices and a widely used networking layer. In addition, it provides a
rich set of peripherals that operate in accordance with several industry standards,
such as those used in audio, telecommunication, Flash Card, infrared and Smart
Card applications.

To complete the offer, the AT91RM9200 benefits from the integration of a wide range of debug features including
JTAG-ICE, a dedicated UART debug channel (DBGU) and an embedded real-time trace. This enables the
development and debug of all applications, especially those with real-time constraints.
Incorporates ARM920T ARM Thumb Processor
̶ 200 MIPS at 180 MHz, Memory Management Unit
̶ 16-Kbyte Data Cache, 16-Kbyte Instruction Cache, Write Buffer
̶ In-circuit Emulator including Debug Communication Channel
̶ Mid-level Implementation Embedded Trace Macrocell(256-ball LFBGA Package only)
Low Power: On VDDCORE 24.4 mA in Normal Mode, 520 µA in Standby Mode
Additional Embedded Memories
̶ 16 Kbytes of SRAM and 128 Kbytes of ROM
External Bus Interface (EBI)
̶ Supports SDRAM, Static Memory, Burst Flash, Glueless Connection to CompactFlash® and NAND
System Peripherals for Enhanced Performance:
̶ Enhanced Clock Generator and Power Management Controller
̶ Two On-chip Oscillators with Two PLLs
̶ Very Slow Clock Operating Mode and Software Power Optimization Capabilities
̶ Four Programmable External Clock Signals
̶ System Timer Including Periodic Interrupt, Watchdog and Second Counter
̶ Real-time Clock with Alarm Interrupt
̶ Debug Unit, Two-wire UART and Support for Debug Communication Channel
̶ Advanced Interrupt Controller with 8-level Priority, Individually Maskable Vectored Interrupt Sources, Spurious
Interrupt Protected
̶ Seven External Interrupt Sources and One Fast Interrupt Source
̶ Four 32-bit PIO Controllers with Up to 122 Programmable I/O Lines, Input Change Interrupt and Open-drain
Capability on Each Line
̶ 20-channel Peripheral DMA Controller (PDC)
Ethernet MAC 10/100 Base-T
̶ Media Independent Interface (MII) or Reduced Media Independent Interface (RMII)
̶ Integrated 28-byte FIFOs and Dedicated DMA Channels for Receive and Transmit
USB 2.0 Full Speed (12 Mbits per second) Host Double Port
̶ Dual On-chip Transceivers (Single Port Only on 208-lead PQFP Package)
̶ Integrated FIFOs and Dedicated DMA Channels
USB 2.0 Full Speed (12 Mbits per second) Device Port
̶ On-chip Transceiver, 2-Kbyte Configurable Integrated FIFOs
Multimedia Card Interface (MCI)
̶ Automatic Protocol Control and Fast Automatic Data Transfers
̶ MMC and SD Memory Card-compliant, Supports Up to Two SD Memory Cards
Three Synchronous Serial Controllers (SSC)
̶ Independent Clock and Frame Sync Signals for Each Receiver and Transmitter
̶ I2S Analog Interface Support, Time Division Multiplex Support
̶ High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer

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