B9948L

B9948L 2.5V/3.3V, 160-MHz, 1:12 Clock Distribution Buffer Product Features 160-MHz clock support 2.5V or 3.3V output capability 200-ps maximum output-to-output skew LVPECL or LVCMOS/LVTTL clock input LVCMOS/LVTTL compatible inputs 12 clock outputs: drive up to 24 clock lines Synchronous Output Enable Output Three-state control Pin compatible with MPC948L Industrial temp. range: –40°C to +85°C 32-pin TQFP package Description The B9948L is a low-voltage clock distribution buffer with the capability to select either a differential LVPECL or a LVCMOS/ LVTTL compatible input clock. The two clock sources can be used to provide for a test clock as well as the primary system clock. All other control inputs are LVCMOS/LVTTL compatible. The twelve outputs are 2.5V or 3.3V LVCMOS or LVTTL compatible and can drive two series-terminated 50Ω transmission lines. With this capability the B9948L has an effective fanout of 1:24. The outputs can also be three-stated via the threestate input TS#. Low output-to-output skews make the B9948L an ideal clock distribution buffer for nested clock trees in the most demanding of synchronous systems. The B9948L also provides a synchronous output enable input for enabling or disabling the output clocks. Since this input is internally synchronized to the input clock, potential output glitching or runt pulse generation is eliminated. Block Diagram Pin Configuration VSS Q0 VDDC Q1 VSS Q2 VDDC Q3 32 31 30 29 28 27 26 25 VDD PECL_CLK ...