BD3531F

Datasheet Termination Regulator for DDR-SDRAMs BD3531F General Description BD3531F is a termination regulator that complies with JEDEC requirements for DDR-SDRAM. This linear power supply uses a built-in N-channel MOSFET and high-speed OP-AMPS specially designed to provide excellent transient response. It has a sink/source current capability up to 1.5A and has a power supply bias requirement of 5.0V for driving the N-channel MOSFET. By employing an independent reference voltage input (VDDQ) and a feedback pin (VTTS), this termination regulator provides excellent output voltage accuracy and load regulation as required by JEDEC standards. Additionally, BD3531F has a reference power supply output (VREF) for DDR-SDRAM or for memory controllers. Unlike the VTT output that goes to “Hi-Z” state, the VREF output is kept unchanged when EN input is changed to “Low”, making this IC suitable for DDR-SDRAM under “Self Refresh” state. Features  Incorporates a Push-Pull Power Supply for Termination (VTT)  Incorporates a Reference Voltage Circuit (VREF)  Incorporates an Enabler  Incorporates an Undervoltage Lockout (UVLO)  Incorporates a Thermal Shutdown Protector (TSD)  Compatible with Dual Channel (DDR-II) Applications Power supply for DDR I/II - SDRAM Key Specifications  Termination Input Voltage Range: 1.0V to 5.5V  VCC Input Voltage Range: 4.5V to 5.5V  Output Voltage: 1/2xVVDDQ V(Typ)  Output Current: 1.5A(Max)  High Side FET ON-Resistance: 0.4Ω(Typ)  Low side ...