BSP121

DISCRETE SEMICONDUCTORS DATA SHEET BSP121 N-channel enhancement mode vertical D-MOS transistor Product specification Supersedes data of April 1995 File under Discrete Semiconductors, SC13b 1998 Apr 01 Philips Semiconductors Product specification N-channel enhancement mode vertical D-MOS transistor DESCRIPTION N-channel enhancement mode vertical D-MOS transistor in a miniature SOT223 envelope and designed for use as a line current interrupter in telephone sets and for application in relay, high-speed and line-transformer drivers. FEATURES Direct interface to C-MOS, TTL, etc. High-speed switching No secondary breakdown PINNING - SOT223 1 = gate 2 = drain 3 = source 4 = drain Marking code BSP121 Transfer admittance ID = 400 mA; VDS = 25 V  Yfs  min. typ. QUICK REFERENCE DATA Drain source voltage Gate-source voltage (open drain) Drain current (DC) Total power dissipation up to Tamb = 25 °C Drain-source on-resistance ID = 400 mA; VGS = 10 V RDS(on) typ. max. Ptot max. VDS ±VGSO ID max. max. max. BSP121 200 V 20 V 350 mA 1.5 W 4.5 Ω 6.0 Ω 200 mS 350 mS PIN CONFIGURATION handbook, halfpage 4 d g 1 Top view 2 3 MAM054 s Fig.1 Simplified outline and symbol. 1998 Apr 01 2 Philips Semiconductors Product specification N-channel enhancement mode vertical D-MOS transistor RATINGS Limiting values in accordance with the Absolute Maximum System (IEC 134) Drain-source voltage Gate-source voltage (open drain) Drain current (DC) Drain current (peak) Total power dissipa...