BSP204A

DISCRETE SEMICONDUCTORS DATA SHEET BSP204; BSP204A P-channel enhancement mode vertical D-MOS transistor Product specification File under Discrete Semiconductors, SC13b April 1995 Philips Semiconductors Product specification P-channel enhancement mode vertical D-MOS transistor FEATURES Direct interface to C-MOS, TTL, etc. High-speed switching No secondary breakdown. DESCRIPTION P-channel enhancement mode vertical D-MOS transistor in a TO-92 variant envelope, intended for use in relay, high-speed and line transformer drivers. PINNING - TO-92 variant (BSP204) PIN 1 2 3 gate drain source DESCRIPTION handbook, halfpage BSP204; BSP204A QUICK REFERENCE DATA SYMBOL −VDS −ID RDS(on) VGS(th) PARAMETER drain-source voltage drain current drain-source on-resistance gate-source threshold voltage DC value −ID = 200 mA −VGS = 10 V −ID = 1 mA VGS = VDS CONDITIONS MAX. 200 250 15 2.8 UNIT V mA Ω V PIN CONFIGURATION 1 d 2 3 g s MAM147 PINNING - TO-92 variant (BSP204A) PIN 1 2 3 gate drain DESCRIPTION source Fig.1 Simplified outline and symbol. April 1995 2 Philips Semiconductors Product specification P-channel enhancement mode vertical D-MOS transistor LIMITING VALUES In accordance with the Absolute Maximum System (IEC 134). SYMBOL −VDS ±VGSO −ID −IDM Ptot Tstg Tj Note PARAMETER drain-source voltage gate-source voltage drain current drain current total power dissipation storage temperature range junction temperature DC value peak value up to Tamb = 25 °C (note 1) CONDITIONS...