BUK542-60A

Philips Semiconductors Product specification PowerMOS transistor Logic level FET GENERAL DESCRIPTION N-channel enhancement mode logic level field-effect power transistor in a plastic full-pack envelope. The device is intended for use in Switched Mode Power Supplies (SMPS), motor control, welding, DC/DC and AC/DC converters, and in automotive and general purpose switching applications. BUK542-60A/B QUICK REFERENCE DATA SYMBOL VDS ID Ptot RDS(ON) PARAMETER BUK542 Drain-source voltage Drain current (DC) Total power dissipation Drain-source on-state resistance; VGS = 5 V MAX. -60A 60 9.2 22 0.15 MAX. -60B 60 8.4 22 0.18 UNIT V A W Ω PINNING - SOT186 PIN 1 2 3 gate drain source DESCRIPTION PIN CONFIGURATION case SYMBOL d g case isolated 1 2 3 s LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL VDS VDGR ±VGS ±VGSM ID ID IDM Ptot Tstg Tj PARAMETER Drain-source voltage Drain-gate voltage Gate-source voltage Non-repetitive gate-source voltage Drain current (DC) Drain current (DC) Drain current (pulse peak value) Total power dissipation Storage temperature Junction Temperature CONDITIONS RGS = 20 kΩ tp ≤ 50 µs Ths = 25 ˚C Ths = 100 ˚C Ths = 25 ˚C Ths = 25 ˚C MIN. - 55 -60A 9.2 5.8 37 22 150 150 MAX. 60 60 15 20 -60B 8.4 5.3 33 UNIT V V V V A A A W ˚C ˚C THERMAL RESISTANCES SYMBOL Rth j-hs Rth j-a PARAMETER Thermal resistance junction to heatsink Thermal resistance junction to ambient CONDITIONS with heatsink compound MIN. TYP. 5...