Philips Semiconductors
Product specification
PowerMOS transistor Logic level FET
GENERAL DESCRIPTION
N-channel enhance...
Philips Semiconductors
Product specification
PowerMOS transistor Logic level FET
GENERAL DESCRIPTION
N-channel enhancement mode logic level field-effect power transistor in a plastic full-pack envelope. The device is intended for use in Automotive applications, Switched Mode Power Supplies (SMPS), motor control, welding, DC/DC and AC/DC converters, and in general purpose switching applications.
BUK545-60H
QUICK REFERENCE DATA
SYMBOL VDS ID Ptot Tj RDS(ON) PARAMETER Drain-source
voltage Drain current (DC) Total power dissipation Junction temperature Drain-source on-state resistance; VGS = 5 V MAX. 60 21 30 150 38 UNIT V A W ˚C mΩ
PINNING - SOT186
PIN 1 2 3 gate drain DESCRIPTION
PIN CONFIGURATION
case
SYMBOL
d
g
source
1 2 3
case isolated
s
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL VDS VDGR ±VGS ±VGSM ID ID IDM Ptot Tstg Tj PARAMETER Drain-source
voltage Drain-gate
voltage Gate-source
voltage Non-repetitive gate-source
voltage Drain current (DC) Drain current (DC) Drain current (pulse peak value) Total power dissipation Storage temperature Junction Temperature CONDITIONS RGS = 20 kΩ tp ≤ 50 µs Ths = 25 ˚C Ths = 100 ˚C Ths = 25 ˚C Ths = 25 ˚C MIN. - 55 MAX. 60 60 15 20 21 13.5 82 30 150 150 UNIT V V V V A A A W ˚C ˚C
THERMAL RESISTANCES
SYMBOL Rth j-hs Rth j-a PARAMETER Thermal resistance junction to heatsink Thermal resistance junction to ambient CONDITIONS With heatsink compound TYP. 55 MAX. 4.17 UNIT K/W K/W
...