BUK573-48C

Philips Semiconductors Product specification PowerMOS transistor Clamped logic level FET GENERAL DESCRIPTION Protected N-channel enhancement mode logic level field-effect power transistor in a plastic full-pack envelope. The device is intended for use in automotive applications. It has built-in zener diodes providing active drain voltage clamping. BUK573-48C QUICK REFERENCE DATA SYMBOL V(CL)DSR ID Ptot WDSRR RDS(ON) PARAMETER Drain-source clamp voltage Drain current (DC) Total power dissipation Repetitive clamped turn off energy; Tj = 150˚C Drain-source on-state resistance; VGS = 5 V MIN. 40 TYP. MAX. UNIT 48 58 13 25 50 85 V A W mJ mΩ PINNING - SOT186A PIN 1 2 3 gate drain source DESCRIPTION PIN CONFIGURATION case SYMBOL d g case isolated 1 2 3 s LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL VDS VDG ±VGS ID ID IDM Ptot Tstg Tj PARAMETER Drain-source voltage Drain-gate voltage Gate-source voltage Drain current (DC) Drain current (DC) Drain current (pulse peak value) Total power dissipation Storage temperature Junction Temperature CONDITIONS continuous continuous Ths = 25 ˚C Ths = 100 ˚C Ths = 25 ˚C Ths = 25 ˚C MIN. - 55 - 55 MAX. 30 30 15 13 8.2 52 25 150 150 UNIT V V V A A A W ˚C ˚C THERMAL RESISTANCES SYMBOL Rth j-hs Rth j-a PARAMETER Thermal resistance junction to heatsink Thermal resistance junction to ambient CONDITIONS with heatsink compound MIN. TYP. 55 MAX. 5 UNIT K/W K/W August 1994 1 Rev 1.000 Philip...