BUK9K6R2-40E
Dual N-channel TrenchMOS logic level FET
23 April 2013
Product data sheet
1. General description
Dual log...
BUK9K6R2-40E
Dual N-channel TrenchMOS logic level FET
23 April 2013
Product data sheet
1. General description
Dual logic level N-channel
MOSFET in a LFPAK56D package using TrenchMOS technology. This product has been designed and qualified to AEC Q101 standard for use in high performance automotive applications.
2. Features and benefits
Q101 compliant Repetitive avalanche rated Suitable for thermally demanding environments due to 175 °C rating True logic level gate with VGS(th) > 0.5 V @ 175 °C
3. Applications
12 V Automotive systems Motors, lamps and solenoid control Start-stop micro-hybrid applications Transmission control Ultra high performance power switching
4. Quick reference data
Table 1. Quick reference data
Symbol
Parameter
Conditions
VDS drain-source
voltage Tj ≥ 25 °C; Tj ≤ 175 °C
ID
drain current
VGS = 5 V; Tmb = 25 °C; Fig. 1
Ptot total power dissipation Tmb = 25 °C; Fig. 2
Static characteristics FET1 and FET2
RDSon
drain-source on-state VGS = 5 V; ID = 20 A; Tj = 25 °C; Fig. 12 resistance
Dynamic characteristics FET1 and FET2
QGD
gate-drain charge
ID = 10 A; VDS = 32 V; VGS = 10 V;
Tj = 25 °C; Fig. 14; Fig. 15
Min Typ Max Unit - - 40 V - - 40 A - - 68 W
- 5.27 6.2 mΩ
- 5.8 - nC
Nexperia
BUK9K6R2-40E
Dual N-channel TrenchMOS logic level FET
5. Pinning information
Table 2. Pinning information Pin Symbol Description 1 S1 source1 2 G1 gate1 3 S2 source2 4 G2 gate2 5 D2 drain2 6 D2 drain2 7 D1 drain1 8 D1 drain1
Simplified ...