Gate. CD4030C Datasheet

CD4030C Datasheet PDF

Part CD4030C
Description Quad EXCLUSIVE-OR Gate
Feature CD4030C; CD4030M CD4030C Quad EXCLUSIVE-OR Gate February 1988 CD4030M CD4030C Quad EXCLUSIVE-OR Gate Genera.
Manufacture National Semiconductor
Datasheet
Download CD4030C Datasheet

CD4030M CD4030C Quad EXCLUSIVE-OR Gate February 1988 CD403 CD4030C Datasheet





CD4030C
February 1988
CD4030M CD4030C Quad EXCLUSIVE-OR Gate
General Description
The EXCLUSIVE-OR gates are monolithic complementary
MOS (CMOS) integrated circuits constructed with N- and P-
channel enhancement mode transistors All inputs are pro-
tected against static discharge with diodes to VDD and VSS
Features
Y Wide supply voltage range
Y Low power
Y Medium speed
operation
Y High noise immunity
3 0V to 15V
100 nW (typ )
tPHL e tPLH e 40 ns (typ )
at CL e 15 pF 10V supply
0 45 VCC (typ )
Applications
Y Automotive
Y Data terminals
Y Instrumentation
Y Medical electronics
Y Industrial controls
Y Remote metering
Y Computers
Schematic Diagram
Connection Diagram
Dual-In-Line Package
TL F 5961 – 1
C1995 National Semiconductor Corporation TL F 5961
Order Number CD4030
TL F 5961 – 2
RRD-B30M105 Printed in U S A



CD4030C
Absolute Maximum Ratings
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Voltage at Any Pin (Note 1)
VSS b0 3V to VSS a15 5V
Operating Temperature Range
CD4030M
b55 C to a125 C
CD4030C
b40 C to a85 C
Storage Temperature Range
Power Dissipation (PD)
Dual-In-Line
Small Outline
Operating VDD Range
Lead Temperature
(Soldering 10 seconds)
b65 C to a150 C
700 mW
500 mW
VSS a3 0V to VSS a15V
260 C
DC Electrical Characteristics CD4030M
Limits
Symbol
Parameter
Conditions
b55 C
a25 C
a125 C
Units
Min Typ Max Min Typ Max Min Typ Max
IL
PD
VOL
VOH
VNL
VNH
IDN
IDP
II
Quiescent Device
Current
Quiescent Device
Dissipation Package
Output Voltage
Low Level
Output Voltage
High Level
Noise Immunity
(All Inputs)
Noise Immunity
(All Inputs)
Output Drive Current
N-Channel (Note 2)
Output Drive Current
P-Channel (Note 2)
Input Current
VDD e 5 0V
VDD e 10V
VDD e 5 0V
VDD e 10V
VDD e 5 0V
VDD e 10V
VDD e 5 0V
VDD e 10V
VDD e 5 0V
VDD e 10V
VDD e 5 0V
VDD e 10V
VDD e 5 0V
VDD e 10V
VDD e 5 0V
VDD e 10V
VI e 0V or VI e VDD
4 95
9 95
15
30
14
29
0 75
15
b0 45
b0 95
0 5 0 005 0 5
1 0 0 01 1 0
2 5 0 025 2 5
10 0 1 10
0 05 0 0 05
0 05 0 0 05
4 95 5 0
9 95 10
4 95
9 95
1 5 2 25
30 45
14
29
1 5 2 25
30 45
15
30
06 12
12 24
0 45
09
b0 3 b0 6
b0 65 b1 3
b0 21
b0 45
10
30
60
150
600
0 05
0 05
mA
mA
mW
mW
V
V
V
V
V
V
V
V
mA
mA
mA
mA
pA
DC Electrical Characteristics CD4030C
Limits
Symbol
Parameter
Conditions
b40 C
a25 C
a85 C
Units
Min Typ Max Min Typ Max Min Typ Max
IL
PD
VOL
VOH
VNL
VNH
IDN
IDP
II
Quiescent Device
Current
Quiescent Device
Dissipation Package
Output Voltage
Low Level
Output Voltage
High Level
Noise Immunity
(All Inputs)
Noise Immunity
(All Inputs)
Output Drive Current
N-Channel (Note 2)
Output Drive Current
P-Channel (Note 2)
Input Current
VDD e 5 0V
VDD e 10V
VDD e 5 0V
VDD e 10V
VDD e 5 0V
VDD e 10V
VDD e 5 0V
VDD e 10V
VDD e 5 0V
VDD e 10V
VDD e 5 0V
VDD e 10V
VDD e 5 0V
VDD e 10V
VDD e 5 0V
VDD e 10 V
VI e 0V or VI e VDD
4 95
9 95
15
30
14
29
0 35
07
b0 21
b0 45
5 0 0 05 5 0
10 0 1 10
25 0 25 25
100 1 0 100
0 05 0 0 05
0 05 0 0 05
4 95 5 0
9 95 10
4 95
9 95
1 5 2 25
30 45
14
29
1 5 2 25
30 45
15
30
03 12
06 24
0 25
05
b0 15 b0 6
b0 32 b1 3
b0 12
b0 25
10
70
140
350
1 400
0 05
0 05
mA
mA
mW
mW
V
V
V
V
V
V
V
V
mA
mA
mA
mA
pA
2



CD4030C
AC Electrical Characteristics CD4030M
Symbol
Parameter
tPHL
Propagation Delay Time
tPLH
Propagation Delay Time
tTHL
Transition Time
High to Low Level
tTLH
Transition Time
Low to High Level
CI Input Capacitance
AC Parameters are guaranteed by DC correlated testing
Conditions
VDD e 5 0V
VDD e 10V
VDD e 5 0V
VDD e 10V
VDD e 5 0V
VDD e 10V
VDD e 5 0V
VDD e 10V
VI e 0V or VI e VDD
Limits
Min Typ Max
100 200
40 100
100 200
40 100
70 150
25 75
80 150
30 75
50
AC Electrical Characteristics CD4030C
Symbol
Parameter
Conditions
Limits
Min Typ Max
tPHL
Propagation Delay Time
VDD e 5 0V
VDD e 10V
100 300
40 150
tPLH
Propagation Delay Time
VDD e 5 0V
VDD e 10V
100 300
40 150
tTHL
Transition Time
High to Low Level
VDD e 5 0V
VDD e 10V
70 300
25 150
tTLH
Transition Time
Low to High Level
VDD e 5 0V
VDD e 10V
80 300
30 150
CI Input Capacitance VI e 0V or VI e VDD
50
AC Parameters are guaranteed by DC correlated testing
Note 1 This device should not be connected to circuits with power on because high transient voltages may cause permanent damage
Note 2 IDN and IDP are tested one output at a time
Truth Table (For One of Four Identical Gates)
AB
00
10
01
11
Where ‘‘1’’ e High Level
‘‘0’’ e Low Level
J
0
1
1
0
Units
ns
ns
ns
ns
ns
ns
ns
ns
pF
Units
ns
ns
ns
ns
ns
ns
ns
ns
pF
3






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