CD54HC297

Data sheet acquired from Harris Semiconductor SCHS177B November 1997 - Revised May 2003 CD54HC297, CD74HC297, CD74HCT297 High-Speed CMOS Logic Digital Phase-Locked Loop [ /Title (CD74 HC297 , CD74 HCT29 7) /Subject (HighSpeed CMOS Logic Digital PhaseLocked Features Description Digital Design Avoids Analog Compensation Errors Easily Cascadable for Higher Order Loops Useful Frequency Range - K-Clock . . . . . . . . . . . . . . . . . . . . . . . . . .DC to 55MHz (Typ) - I/D-Clock . . . . . . . . . . . . . . . . . . . . DC to 35MHz (Typ) Dynamically Variable Bandwidth Very Narrow Bandwidth Attainable Power-On Reset Output Capability - Standard . . . . . . . . . . . . . . . . . . . . XORPDOUT, ECPDOUT - Bus Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/DOUT Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads Balanced Propagation Delay and Transition Times Significant Power Reduction Compared to LSTTL Logic ICs ’HC297 Types - Operation Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 to 6V - High Noise Immunity NIL = 30%, NIH = 30% of VCC at 5V CD74HCT297 Types - Operation Voltage . . . . . . . . . . . . . . . . . . . . . . . . 4.5 to 5.5V - Direct LSTTL Input Logic Compatibility VIL = 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility II ≤ 1µA at VOL, VOH Pinout CD54HC297 (CERDIP) CD74HC297, CD74HCT29 ...