D 2-V to 6-V Operation D Fully Static Operation D Buffered Inputs D Common Reset D Positive-Edge Clocking D Balanced Pro...
D 2-V to 6-V Operation D Fully Static Operation D Buffered Inputs D Common Reset D Positive-Edge Clocking D Balanced Propagation Delay and Transition
Times
D High Noise Immunity: NIL = 30%, NIH = 30%
of VCC at VCC = 5 V
D Packaged in Ceramic (F) DIP Package and
Also Available in Chip Form (H)
CD54HC4017 DECADE COUNTER/DIVIDER WITH TEN DECODED OUTPUTS
SGDS011 – MAY 1999
F PACKAGE (TOP VIEW)
51 12 03 24 65 76 37 GND 8
16 VCC 15 MR 14 CP 13 CE 12 TC 11 9 10 4 98
description
The CD54HC4017 is a high-speed silicon-gate
CMOS 5-stage Johnson counter with ten decoded outputs. Each decoded output normally is low and sequentially goes high on the low-to-high transition of the clock (CP) input. Each output stays high for one clock period of the ten-clock-period cycle. The terminal count (TC) output transitions low to high after output ten (9) goes low, and can be used in conjunction with the clock enable (CE) input to cascade several stages. CE disables counting when in the high state. The master reset (MR) input, when taken high, sets all the decoded outputs, except 0, to low.
The CD54HC4017 is characterized for operation over the full military temperature range of –55°C to 125°C.
FUNCTION TABLE
INPUTS CP CE MR
OUTPUT STATE†
L
X
L
No change
X
H
L
No change
X
X
H
0=H 1–9 = L
↑
L
L Increments counter
↓
X
L
No change
X
↑
L
No change
H
↓
L Increments counter
† If n < 5, TC = H; otherwise, TC = L.
Please be aware that an important notice concerning availab...
