CD54HC273, CD74HC273 CD54HCT273, CD74HCT273
SCHS174C – FEBRUARY 1998 – REVISED JANUARY 2022
CDx4HC(T)273 High-Speed CMOS...
CD54HC273, CD74HC273 CD54HCT273, CD74HCT273
SCHS174C – FEBRUARY 1998 – REVISED JANUARY 2022
CDx4HC(T)273 High-Speed
CMOS Logic Octal D-Type Flip-Flop with Reset
1 Features
Common clock and asynchronous controller reset Positive edge triggering Buffered inputs Fanout (over temperature range)
– Standard outputs: 10 LSTTL loads – Bus driver outputs: 15 LSTTL loads Wide operating temperature range: –55℃ to 125℃ Balanced propagation delay and transition times Significant power reduction compared to LSTTL Logic ICs HC types:
– 2 V to 6 V operation – High noise immunity: NIL = 30%, NIH = 30% of
VCC at VCC = 5V HCT types:
– 4.5 V to 5.5 V operation – Direct LSTTL input logic compatibility, VIL = 0.8
V (max), VIH = 2 V (min) –
CMOS input compatibility, II ≤ 1 μA at VOL,VOH
2 Description
The ’HC273 and ’HCT273 high speed octal D-Type flip-flops with a direct clear input are manufactured with silicon-gate
CMOS technology. They possess the low power consumption of standard
CMOS integrated circuits.
Information at the D input is transferred to the Q outputs on the positive-going edge of the clock pulse. All eight flip-flops are controlled by a common clock (CLK) and a common reset (CLR). Resetting is accomplished by a low
voltage level independent of the clock. All eight Q outputs are reset to a logic 0.
PART NUMBER CD54HC273F CD74HC273M CD74HC273E CD74HCT273M CD74HCT273
Device Information
PACKAGE(1) BODY SIZE (NOM)
CDIP (20)
26.92 mm × 6.92 mm
SOIC (20)
12.80 ...
