CD54HCT373

CD54HCT373, CD74HCT373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS453B – FEBRUARY 2001 – REVISED MAY 2003 D 4.5-V to 5.5-V VCC Operation D Wide Operating Temperature Range of –55°C to 125°C D Balanced Propagation Delays and Transition Times D Standard Outputs Drive Up To 10 LS-TTL Loads D Significant Power Reduction Compared to LS-TTL Logic ICs D Inputs Are TTL-Voltage Compatible description/ordering information The ’HCT373 devices are octal transparent D-type latches. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is low, the Q outputs are latched at the logic levels of the D inputs. CD54HCT373 . . . F PACKAGE CD74HCT373 . . . E OR M PACKAGE (TOP VIEW) OE 1 1Q 2 1D 3 2D 4 2Q 5 3Q 6 3D 7 4D 8 4Q 9 GND 10 20 VCC 19 8Q 18 8D 17 7D 16 7Q 15 6Q 14 6D 13 5D 12 5Q 11 LE A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minim...