CD74HC259

CD54HC259, CD74HC259, CD54HCT259, CD74HCT259 Data sheet acquired from Harris Semiconductor SCHS173C November 1997 - Revised October 2003 High-Speed CMOS Logic 8-Bit Addressable Latch [ /Title (CD74 HC259 , CD74 HCT25 9) /Subject (High Speed CMOS Logic 8-Bit Addres sable Latch) Features Description Buffered Inputs and Outputs Four Operating Modes Typical Propagation Delay CL = 15pF, TA = 25oC of 15ns at VCC = 5V, Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads Wide Operating Temperature Range . . . -55oC to 125oC Balanced Propagation Delay and Transition Times Significant Power Reduction Compared to LSTTL Logic ICs HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH The ’HC259 and ’HCT259 Addressable Latch features the low-power consumption associated with CMOS circuitry and has speeds comparable to low-power Schottky. This latches three active modes and one reset mode. When both the Latch Enable (LE) and Master Reset (MR) inputs are low (8-line Demultiplexer mode) the output of the addressed latch follows the Data input and all other outputs are forced low. When both MR and LE are high (Memory Mode), all outputs are isolated from the...