Data sheet acquired from Harris Semiconductor SCHS184C
September 1997 - Revised February 2004
CD54HC377, CD74HC377, CD5...
Data sheet acquired from Harris Semiconductor SCHS184C
September 1997 - Revised February 2004
CD54HC377, CD74HC377, CD54HCT377, CD74HCT377
High-Speed
CMOS Logic Octal D-Type Flip-Flop With Data Enable
[ /Title (CD74 HC377 , CD74 HCT37 7) /Subject (High Speed
CMOS Logic Octal DType Flip-
Features
Description
Buffered Common Clock
Buffered Inputs
Typical Propagation VCC = 5V, TA = 25oC
Delay
at
CL
=
15pF,
- 14 ns (HC Types
- 16 ns (HCT Types)
Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads Wide Operating Temperature Range . . . -55oC to 125oC
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to LSTTL Logic ICs
HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30%of VCC at VCC = 5V
HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) -
CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
The ’HC377 and ’HCT377 are octal D-type flip-flops with a buffered clock (CP) common to all eight flip-flops. All the flipflops are loaded simultaneously on the positive edge of the clock (CP) when the Data Enable (E) is Low.
Ordering Information
PART NUMBER
TEMP. RANGE (oC)
PACKAGE
CD54HC377F3A
-55 to 125
20 Ld CERDIP
CD54HCT377F3A
-55 to 125
20 Ld CERDIP
CD74HC377E
-55 to 125
20 Ld PDIP
CD74HC377M
-55 to 125
20 Ld SOIC
CD74HC377M96
-...