CD74HCT191

CD54HC190, CD74HC190 CD54HC191, CD74HC191, CD54HCT191, CD74HCT191 SYNCHRONOUS UP/DOWN COUNTERS WITH DOWN/UP MODE CONTROL SCHS275E − MARCH 2002 − REVISED OCTOBER 2003 D 2-V to 6-V VCC Operation (’HC190, 191) D 4.5-V to 5.5-V VCC Operation (’HCT191) D Wide Operating Temperature Range of −55°C to 125°C D Synchronous Counting and Asynchronous Loading D Two Outputs for n-Bit Cascading D Look-Ahead Carry for High-Speed Counting D Balanced Propagation Delays and Transition Times D Standard Outputs Drive Up To 15 LS-TTL Loads D Significant Power Reduction Compared to LS-TTL Logic ICs CD54HC190, 191; CD54HCT191 . . . F PACKAGE CD74HC190 . . . E, NS, OR PW PACKAGE CD74HC191, CD74HCT191 . . . E OR M PACKAGE (TOP VIEW) B QB QA CTEN D/U QC QD GND 1 2 3 4 5 6 7 8 16 VCC 15 A 14 CLK 13 RCO 12 MAX/MIN 11 LOAD 10 C 9D description/ordering information The CD54/74HC190 are asynchronously presettable BCD decade counters, whereas the CD54/74HC191 and CD54/74HCT191 are asynchronously presettable binary counters. Presetting the counter to the number on preset data inputs (A−D) is accomplished by a low asynchronous parallel load (LOAD) input. Counting occurs when LOAD is high, count enable (CTEN) is low, and the down/up (D/U) input is either high for down counting or low for up counting. The counter is decremented or incremented synchronously with the low-to-high transition of the clock. ORDERING INFORMATION TA PACKAGE† ORDERABLE PART NUMBER TOP-SIDE MARKING CD74HC190E CD74HC190E PDIP ...