CDC5801A

CDC5801A LOW JITTER CLOCK MULTIPLIER AND DIVIDER WITH PROGRAMMABLE DELAY AND PHASE ALIGNMENT SCAS813A − AUGUST 2005 − REVISED DECEMBER 2005 D Low Jitter Clock Multiplier by x4, x6, x8. Input Frequency Range (19 MHz to 125 MHz). Supports Output Frequency From 150 MHz to 500 MHz D Fail-Safe Power Up Initialization D Low Jitter Clock Divider by /2, /3, /4. Input Frequency Range (50 MHz to 125 MHz). Supports Ranges of Output Frequency From 12.5 MHz to 62.5 MHz D 2.6 mUI Programmable Bidirectional Delay Steps D Typical 8-ps Phase Jitter (12 kHz to 20 MHz) at 500 MHz D Typical 2.1-ps RMS Period Jitter (Entire Frequency Band) at 500 MHz D One Single-Ended Input and One Differential Output Pair D Output Can Drive LVPECL, LVDS, and LVTTL D Three Power Operating Modes to Minimize Power D Low Power Consumption (Typical 200 mW at 500 MHz) D Packaged in a Shrink Small-Outline Package (DBQ) D No External Components Required for PLL D Spread Spectrum Clock Tracking Ability to Reduce EMI D Applications: Video Graphics, Gaming Products, Datacom, Telecom D Accepts LVCMOS, LVTTL Inputs for REFCLK Terminal D Accepts Other Single-Ended Signal Levels at REFCLK Terminal by Programming Proper VDDREF Voltage Level (For Example, HSTL 1.5 if VDDREF = 1.6 V) D Supports Industrial Temperature Range of −40°C to 85°C DBQ PACKAGE (TOP VIEW) VDDREF 1 REFCLK 2 VDDP 3 GNDP 4 GND 5 LEADLAG 6 DLYCTRL 7 GNDPA 8 VDDPA 9 VDDPD 10 STOPB 11 PWRDNB 12 24 P0 23 P1 22 VDDO 21 GNDO 20 CLKOUT 19 NC 18 CLKOUTB 17 GNDO...