CDC857-2

CDC857-2, CDC857-3 2.5-/3.3-V PHASE-LOCK LOOP CLOCK DRIVERS SCAS627A – SEPTEMBER 1999 – DECEMBER 1999 D Phase-Lock Loop Clock Distribution for Double Data Rate Synchronous DRAM DGG PACKAGE (TOP VIEW) Applications D Distributes One Differential Clock Input to Ten Differential Outputs D External Feedback Pins (FBIN, FBIN) Are Used to Synchronize the Outputs to the Clock Input D Operates at VCC = 2.5 V and AVCC = 3.3 V D Packaged in Plastic 48-Pin (DGG) Thin Shrink Small-Outline Package (TSSOP) D Spread Spectrum Clocking Tracking GND 1 Y0 2 Y0 3 VCC 4 Y1 5 Y1 6 GND 7 GND 8 Y2 9 Y2 10 48 GND 47 Y5 46 Y5 45 VCC 44 Y6 43 Y6 42 GND 41 GND 40 Y7 39 Y7 Capability to Reduce EMI description VCC 11 VCC 12 CLK 13 38 VCC 37 G 36 FBIN The CDC857-2 and CDC857-3 are high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. They use a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. The CDC857-3 operates at 3.3 V (PLL) and 2.5 V (output buffer). The CDC857-2 operates at 2.5 V (PLL and output buffer). One bank of ten inverting and noninverting outputs provide ten low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to CLK 14 VCC 15 AVCC 16 AGND 17 GND 18 Y3 19 Y3 20 VCC 21 Y4 22 Y4 23 GND 24 35 FBIN 34 VCC 33 FBOUT 32 FBOUT 31 GND 30 Y8 29 Y8 28 VCC 27 Y9 26 Y9 25 GND 50%, independent of the duty cycle at CLK. All outputs can be enabled or disabled via a single output enable i...