CDCE906

CDCE906 www.ti.com SCAS814H – NOVEMBER 2005 – REVISED DECEMBER 2007 PROGRAMMABLE 3-PLL CLOCK SYNTHESIZER / MULTIPLIER / DIVIDER FEATURES 1 2 High Performance 3:6 PLL based Clock Synthesizer / Multiplier / Divider User Programmable PLL Frequencies EEPROM Programming Without the Need to Apply High Programming Voltage Easy In-Circuit Programming via SMBus Data Interface Wide PLL Divider Ratio Allows 0-ppm Output Clock Error Generates Precise Video (27 MHz or 54 MHz) and Audio System Clocks from Multiple Sampling Frequencies (fS = 16, 22.05, 24, 32, 44.1, 48, 96 kHz) Clock Inputs Accept a Crystal or a Single-Ended LVCMOS or a Differential Input Signal Accepts Crystal Frequencies from 8 MHz up to 54 MHz Accepts LVCMOS or Differential Input Frequencies up to 167 MHz Two Programmable Control Inputs [S0/S1, A0/A1] for User Defined Control Signals Six LVCMOS Outputs with Output Frequencies up to 167 MHz LVCMOS Outputs can be Programmed for Complementary Signals Free Selectable Output Frequency via Programmable Output Switching Matrix [6x6] Including 7-Bit Post-Divider for Each Output PLL Loop Filter Components Integrated Low Period Jitter (Typ 60 ps) Features Spread Spectrum Clocking (SSC) for Lowering System EMI Programmable Center Spread SSC Modulation (±0.1%, ±0.25%, and ±0.4%) with a Mean Phase Equal to the Phase of the Non-Modulated Frequency Programmable Down Spread SSC Modulation (1%, 1.5%, 2%, and 3%) Programmable Output Slew-Rate Cont...