CDCF5801

Not Recommended for New Designs CDCF5801 www.ti.com SCAS698F – SEPTEMBER 2003 – REVISED APRIL 2006 CLOCK MULTIPLIER WITH DELAY CONTROL AND PHASE ALIGNMENT (Not Recommended for New Designs Use CDCF5801A as a Replacement) FEATURES Low-Jitter Clock Multiplier: ×1, ×2, ×4, ×8 Programmable Bidirectional Delay Steps of 1.3 mUI Output Frequency Range of 25 MHz to 280 MHz Input Frequency Range of 12.5 MHz to 240 MHz Low Jitter Generation Single-Ended REFCLK Input With Adjustable Trigger Level (Works With LVTTL, HSTL, and LVPECL) Differential/Single-Ended Output Output Can Drive LVPECL, LVDS, and LVTTL Three Power Operating Modes to Minimize Power Low Power Consumption (< 190 mW at 280 MHz/3.3 V) Packaged in a Shrink Small-Outline Package (DBQ) No External Components Required for PLL Spread Spectrum Clock Tracking Ability to Reduce EMI (SSC) APPLICATIONS Video Graphics Gaming Products Datacom Telecom Noise Cancellation Created by FPGAs DBQ PACKAGE (TOP VIEW) VDDREF 1 REFCLK 2 VDDP 3 GNDP 4 GND 5 LEADLAG 6 DLYCTRL 7 GNDPA 8 VDDPA 9 VDDPD 10 STOPB 11 PWRDNB 12 24 P0 23 P1 22 VDDO 21 GNDO 20 CLKOUT 19 NC 18 CLKOUTB 17 GNDO 16 VDDO 15 MULT0 14 MULT1 13 P2 DESCRIPTION The CDCF5801 provides clock multiplication from a reference clock (REFCLK) signal with the unique capability to delay or advance the CLKOUT/CLKOUTB with steps of only 1.3 mUI through a phase aligner. For every rising edge on the DLYCTRL...