CDCL1810A

Product Folder Sample & Buy Technical Documents Tools & Software Support & Community CDCL1810A SLLSEL1 – NOVEMBER 2014 CDCL1810A 1.8V, 10 Output, High-Performance Clock Distributor 1 Features 1 Single 1.8 V Supply High-Performance Clock Distributor with 10 Outputs Low Input-to-Output Additive Jitter: as low as 10fs RMS Low-Voltage Differential Signaling (LVDS) Input, 100Ω Differential On-Chip Termination, up to 650 MHz Frequency Differential Current Mode Logic (CML) Outputs, 50Ω Single-Ended On-Chip Termination, up to 650 MHz Frequency Two Groups of Five Outputs Each with Independent Frequency Division Ratios Output Frequency Derived with Divide Ratios of 1, 2, 4, 5, 8, 10, 16, 20, 32, 40, and 80 Meets ANSI TIA/EIA-644-A-2001 LVDS Standard Requirements Power Consumption: 410 mW Typical Output Enable Control for Each Output SDA/SCL Device Management Interface 48-pin VQFN (RGZ) Package Industrial Temperature Range: –40°C to +85°C 2 Applications Clock Distribution for High-Speed SERDES Distribution of SERDES Reference Clocks for 1G/10G Ethernet, 1X/2X/4X/10X Fibre Channel, PCI Express, Serial ATA, SONET, CPRI, OBSAI, and so forth Up to 1-to-10 Clock Buffering and Fan-out 3 Description The CDCL1810A is a high-performance clock distributor. The programmable dividers, P0 and P1, give a high flexibility to the ratio of the output frequency to the input frequency: FOUT = FIN/P, where P (P0,P1) = 1, 2, 4, 5, 8, 10, 16, 20, 32, 40, 80. The CDCL1810...