www.ti.com
CDCLVD110
SCAS684C – SEPTEMBER 2002 – REVISED JANUARY 2008
Not Recommended for New Designs
PROGRAMMABLE LO...
www.ti.com
CDCLVD110
SCAS684C – SEPTEMBER 2002 – REVISED JANUARY 2008
Not Recommended for New Designs
PROGRAMMABLE LOW-
VOLTAGE 1:10 LVDS CLOCK DRIVER
FEATURES
1
Low-Output Skew <30 ps (Typical) for Clock-Distribution Applications
Distributes One Differential Clock Input to 10 LVDS Differential Clock Outputs
VCC range 2.5 V ±5% Typical Signaling Rate Capability of Up to
1.1 GHz
Configurable Register (SI/CK) Individually Enables Disables Outputs, Selectable CLK0, CLK0 or CLK1, CLK1 Inputs
Full Rail-to-Rail Common-Mode Input Range Receiver Input Threshold ±100 mV Available in 32-Pin LQFP Package Fail-Safe I/O-Pins for VDD = 0 V (Power Down)
LQFP PACKAGE
DESCRIPTION
The CDCLVD110 clock driver distributes one pair of differential LVDS clock inputs (either CLK0 or CLK1) to 10 pairs of differential clock outputs (Q0, Q9) with minimum skew for clock distribution. The CDCLVD110 is specifically designed for driving 50-Ω transmission lines.
When the control enable is high (EN = 1), the 10 differential outputs are programmable in that each output can be individually enabled/disabled (3-stated) according to the first 10 bits loaded into the shift register. Once the shift register is loaded, the last bit selects either CLK0 or CLK1 as the clock input. However, when EN = 0, the outputs are not programmable and all outputs are enabled.
The CDCLVD110 is characterized for operation from –40°C to 85°C.
Not Recommended for New Designs. Use CDCLVD110A as a Replacement.
1
...