CDCLVP1212

Product Folder Sample & Buy Technical Documents Tools & Software Support & Community CDCLVP1212 SCAS886E – AUGUST 2009 – REVISED DECEMBER 2015 CDCLVP1212 LVPECL Output, High-Performance Clock Buffer 1 Features 1 2:12 Differential Buffer Selectable Clock Inputs Through Control Terminal Universal Inputs Accept LVPECL, LVDS, and LVCMOS/LVTTL 12 LVPECL Outputs Maximum Clock Frequency: 2 GHz Maximum Core Current Consumption: 88 mA Very Low Additive Jitter: <100 fs, rms in 10-kHz to 20-MHz Offset Range: – 57 fs, rms (typ) @ 122.88 MHz – 48 fs, rms (typ) @ 156.25 MHz – 30 fs, rms (typ) @ 312.5 MHz 2.375-V to 3.6-V Device Power Supply Maximum Propagation Delay: 550 ps Maximum Output Skew: 25 ps LVPECL Reference Voltage, VAC_REF, Available for Capacitive-Coupled Inputs Industrial Temperature Range: –40°C to 85°C ESD Protection Exceeds 2 kV (HBM) Supports 105°C PCB Temperature (Measured with a Thermal Pad) Available in 6-mm × 6-mm QFN-40 (RHA) Package 2 Applications Wireless Communications Telecommunications/Networking Medical Imaging Test and Measurement Equipment INP0 INN0 INP1 INN1 IN_SEL VAC_REF Functional Block Diagram VCC VCC VCC VCC VCC VCC IN_MUX LVPECL OUTP[11...0] 12 OUTN[11...0] 12 Reference Generator GND GND 3 Description The CDCLVP1212 is a highly versatile, low additive jitter buffer that can generate 12 copies of LVPECL clock outputs from one of two selectable LVPECL, LVDS, or LVCMOS inputs for a variety of commun...