CDCLVP2102

Product Folder Sample & Buy Technical Documents Tools & Software Support & Community CDCLVP2102 SCAS881C – AUGUST 2009 – REVISED JANUARY 2016 CDCLVP2102 Four-LVPECL Output, High-Performance Clock Buffer 1 Features 1 Dual 1:2 Differential Buffer Two Clock Inputs Universal Inputs Can Accept LVPECL, LVDS, LVCMOS/LVTTL Four LVPECL Outputs Maximum Clock Frequency: 2 GHz Maximum Core Current Consumption: 48 mA Very Low Additive Jitter: <100 fs, RMS in 10-kHz to 20-MHz Offset Range 2.375-V to 3.6-V Device Power Supply Maximum Propagation Delay: 450 ps Maximum Within Bank Output Skew: 10 ps LVPECL Reference Voltage, VAC_REF, Available for Capacitive-Coupled Inputs Industrial Temperature Range: –40°C to +85°C Supports 105°C PCB Temperature (Measured with a Thermal Pad) Available in 3-mm × 3-mm, 16-Pin VQFN (RGT) Package ESD Protection Exceeds 2000 V (HBM) 2 Applications Wireless Communications Telecommunications/Networking Medical Imaging Test and Measurement Equipment 3 Description The CDCLVP2102 is a highly versatile, low additive jitter buffer that can generate four copies of LVPECL clock outputs from two LVPECL, LVDS, or LVCMOS inputs for a variety of communication applications. It has a maximum clock frequency up to 2 GHz. Each buffer block consists of one input that feeds two LVPECL outputs. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to 20 MHz, and overall output skew is as low as 10 ps, making the dev...