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CDCU877B Datasheet

Part Number CDCU877B
Manufacturers Texas Instruments
Logo Texas Instruments
Description 1.8-V PHASE LOCK LOOP CLOCK DRIVER
Datasheet CDCU877B DatasheetCDCU877B Datasheet (PDF)

CDCU877B www.ti.com FEATURES • 1.8-V Phase Lock Loop Clock Driver for Double Data Rate (DDR II) Applications • Spread Spectrum Clock Compatible • Operating Frequency: 10 MHz to 340 MHz • Low Current Consumption: <115 mA • Low Jitter (Cycle-Cycle): ±30 ps • Low Output Skew: 25 ps • Low Period Jitter: ±20 ps 1.8-V PHASE LOCK LOOP CLOCK DRIVER SCAS801B – JUNE 2005 – REVISED JULY 2007 • Low Dynamic Phase Offset: ±15 ps • Low Static Phase Offset: ±50 ps • Distributes One Differential Clock Input to.

  CDCU877B   CDCU877B






Part Number CDCU877A
Manufacturers Texas Instruments
Logo Texas Instruments
Description 1.8-V PHASE LOCK LOOP CLOCK DRIVER
Datasheet CDCU877B DatasheetCDCU877A Datasheet (PDF)

CDCU877, CDCU877A www.ti.com FEATURES • 1.8-V Phase Lock Loop Clock Driver for Double Data Rate (DDR II) Applications • Spread Spectrum Clock Compatible • Operating Frequency: 10 MHz to 400 MHz • Low Current Consumption: <135 mA • Low Jitter (Cycle-Cycle): ±30 ps • Low Output Skew: 35 ps • Low Period Jitter: ±20 ps • Low Dynamic Phase Offset: ±15 ps 1.8-V PHASE LOCK LOOP CLOCK DRIVER SCAS688D – JUNE 2005 – REVISED JULY 2007 • Low Static Phase Offset: ±50 ps • Distributes One Differential Clock.

  CDCU877B   CDCU877B







Part Number CDCU877
Manufacturers Texas Instruments
Logo Texas Instruments
Description 1.8-V PHASE LOCK LOOP CLOCK DRIVER
Datasheet CDCU877B DatasheetCDCU877 Datasheet (PDF)

CDCU877, CDCU877A www.ti.com FEATURES • 1.8-V Phase Lock Loop Clock Driver for Double Data Rate (DDR II) Applications • Spread Spectrum Clock Compatible • Operating Frequency: 10 MHz to 400 MHz • Low Current Consumption: <135 mA • Low Jitter (Cycle-Cycle): ±30 ps • Low Output Skew: 35 ps • Low Period Jitter: ±20 ps • Low Dynamic Phase Offset: ±15 ps 1.8-V PHASE LOCK LOOP CLOCK DRIVER SCAS688D – JUNE 2005 – REVISED JULY 2007 • Low Static Phase Offset: ±50 ps • Distributes One Differential Clock.

  CDCU877B   CDCU877B







1.8-V PHASE LOCK LOOP CLOCK DRIVER

CDCU877B www.ti.com FEATURES • 1.8-V Phase Lock Loop Clock Driver for Double Data Rate (DDR II) Applications • Spread Spectrum Clock Compatible • Operating Frequency: 10 MHz to 340 MHz • Low Current Consumption: <115 mA • Low Jitter (Cycle-Cycle): ±30 ps • Low Output Skew: 25 ps • Low Period Jitter: ±20 ps 1.8-V PHASE LOCK LOOP CLOCK DRIVER SCAS801B – JUNE 2005 – REVISED JULY 2007 • Low Dynamic Phase Offset: ±15 ps • Low Static Phase Offset: ±50 ps • Distributes One Differential Clock Input to Ten Differential Outputs • 52-Ball μBGA (MicroStar™ Junior BGA, 0,65-mm pitch) • External Feedback Pins (FBIN, FBIN) are Used to Synchronize the Outputs to the Input Clocks • Fail-Safe Inputs DESCRIPTION The CDCU877B is a high-performance, low-jitter, low-skew, zero-delay buffer that distributes a differential clock input pair (CK, CK) to ten differential pairs of clock outputs (Yn, Yn) and to one differential pair of feedback clock outputs (FBOUT, FBOUT). The clock outputs are controlled by the input clocks (CK, CK), the feedback clocks (FBIN, FBIN), the LVCMOS control pins (OE, OS), and the analog power input (AVDD). When OE is low, the clock outputs, except FBOUT/FBOUT, are disabled while the internal PLL continues to maintain its locked-in frequency. OS (output select) is a program pin that must be tied to GND or VDD. When OS is high, OE functions as previously described. When OS and OE are both low, OE has no affect on Y7/Y7, they are free running. When AVDD is grounded, the PLL.


2023-07-06 : DCP021205    DCP021212    DCP021212D    CDCV850    CDCV850I    CDCV304-EP    CDCV304    CDCUN1208LP    CDCUA877    CDCU877B   


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