CDCVF2509

NOT RECOMMENDED FOR NEW DESIGNS, USE CDCVF2509A AS A REPLACEMENT CDCVF2509 www.ti.com SCAS737D – APRIL 2004 – REVISED FEBRUARY 2010 3.3-V PHASE-LOCK LOOP CLOCK DRIVER Check for Samples: CDCVF2509 FEATURES 1 Use CDCVF2509A (SCAS765) as a Replacement for This Device Designed to Meet and Exceed PC133 SDRAM Registered DIMM Specification Rev. 1.1 Spread Spectrum Clock Compatible Operating Frequency 50 MHz to 175 MHz Static Phase Error Distribution at 66 MHz to 166 MHz Is ±125 ps Jitter (cyc - cyc) at 66 MHz to 166 MHz Is Typ = 70 ps Advanced Deep Submicron Process Results in More Than 40% Lower Power Consumption Versus Current Generation PC133 Devices Available in Plastic 24-Pin TSSOP Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications Distributes One Clock Input to One Bank of Five and One Bank of Four Outputs Separate Output Enable for Each Output Bank External Feedback (FBIN) Terminal Is Used to Synchronize the Outputs to the Clock Input 25-Ω On-Chip Series Damping Resistors No External RC Network Required Operates at 3.3 V APPLICATIONS DRAM Applications PLL Based Clock Distributors Non-PLL Clock Buffer PW PACKAGE (TOP VIEW) AGND 1 VCC 2 1Y0 3 1Y1 4 1Y2 5 GND 6 GND 7 1Y3 8 1Y4 9 VCC 10 1G 11 FBOUT 12 24 CLK 23 AVCC 22 VCC 21 2Y0 20 2Y1 19 GND 18 GND 17 2Y2 16 2Y3 15 VCC 14 2G 13 FBIN DESCRIPTION The CDCVF2509 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely al...