DatasheetsPDF.com

CDCVF2510 Datasheet

Part Number CDCVF2510
Manufacturers Texas Instruments
Logo Texas Instruments
Description 3.3-V PHASE-LOCK LOOP CLOCK DRIVER
Datasheet CDCVF2510 DatasheetCDCVF2510 Datasheet (PDF)

CDCVF2510 www.ti.com SCAS638C – JULY 2001 – REVISED APRIL 2006 3.3-V PHASE-LOCK LOOP CLOCK DRIVER FEATURES • Designed to Meet and Exceed PC133 SDRAM Registered DIMM Specification Rev. 1.1 • Spread Spectrum Clock Compatible • Operating Frequency 50 MHz to 175 MHz • Static Phase Error Distribution at 66 MHz to 166 MHz Is ±125 ps • Jitter (cyc - cyc) at 66 MHz to 166 MHz Is |70| ps • Advanced Deep Submicron Process Results in More Than 40% Lower Power Consumption Versus Current Generation PC133 .

  CDCVF2510   CDCVF2510






Part Number CDCVF2510A
Manufacturers Texas Instruments
Logo Texas Instruments
Description 3.3-V PHASE-LOCK LOOP CLOCK DRIVER
Datasheet CDCVF2510 DatasheetCDCVF2510A Datasheet (PDF)

CDCVF2510A www.ti.com ... SCAS764C – MARCH 2004 – REVISED FEBRUARY 2009 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE FEATURES 1 • Designed to Meet and Exceed PC133 SDRAM Registered DIMM Specification Rev. 1.1 • Spread Spectrum Clock Compatible • Operating Frequency 20 MHz to 175 MHz • Static Phase Error Distribution at 66 MHz to 166 MHz is ±125 ps • Jitter (cyc–cyc) at 66 MHz to 166 MHz is |70| ps • Advanced Deep Submicron Process Results in More Than 40% Lower Power Consumption vs .

  CDCVF2510   CDCVF2510







3.3-V PHASE-LOCK LOOP CLOCK DRIVER

CDCVF2510 www.ti.com SCAS638C – JULY 2001 – REVISED APRIL 2006 3.3-V PHASE-LOCK LOOP CLOCK DRIVER FEATURES • Designed to Meet and Exceed PC133 SDRAM Registered DIMM Specification Rev. 1.1 • Spread Spectrum Clock Compatible • Operating Frequency 50 MHz to 175 MHz • Static Phase Error Distribution at 66 MHz to 166 MHz Is ±125 ps • Jitter (cyc - cyc) at 66 MHz to 166 MHz Is |70| ps • Advanced Deep Submicron Process Results in More Than 40% Lower Power Consumption Versus Current Generation PC133 Devices • Available in Plastic 24-Pin TSSOP • Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications • Distributes One Clock Input to One Bank of 10 Outputs • External Feedback (FBIN) Terminal Is Used to Synchronize the Outputs to the Clock Input • 25-Ω On-Chip Series Damping Resistors • No External RC Network Required • Operates at 3.3 V PW PACKAGE (TOP VIEW) AGND 1 VCC 2 1Y0 3 1Y1 4 1Y2 5 GND 6 GND 7 1Y3 8 1Y4 9 VCC 10 G 11 FBOUT 12 24 CLK 23 AVCC 22 VCC 21 1Y9 20 1Y8 19 GND 18 GND 17 1Y7 16 1Y6 15 1Y5 14 VCC 13 FBIN NOT RECOMMENDED FOR NEW DESIGNS USE CDCVF2510A AS A REPLACEMENT DESCRIPTION The CDCVF2510 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDCVF2510 operates at a 3.3-V VCC. It also provides integrated series-damping r.


2023-07-06 : DCP021205    DCP021212    DCP021212D    CDCV850    CDCV850I    CDCV304-EP    CDCV304    CDCUN1208LP    CDCUA877    CDCU877B   


@ 2014 :: Datasheetspdf.com ::
Semiconductors datasheet search & download site (Privacy Policy & Contact)