DatasheetsPDF.com

CDP1822C Datasheet

Part Number CDP1822C
Manufacturers Intersil Corporation
Logo Intersil Corporation
Description High-Reliability CMOS 256-Word x 4-Bit LSI Static RAM
Datasheet CDP1822C DatasheetCDP1822C Datasheet (PDF)

CDP1822C/3 March 1997 High-Reliability CMOS 256-Word x 4-Bit LSI Static RAM Description The CDP1822C/3 is a 256 word by 4-bit random access memory designed for use in memory systems where high speed, low operating current, and simplicity in use are desirable. The CDP1822 features high speed and excellent noise immunity. It has separate data inputs and outputs and utilizes a single power supply of 4V to 6.5V. Two Chip Select inputs simplify system expansion. An output Disable control provides Wi.

  CDP1822C   CDP1822C






Part Number CDP1822C
Manufacturers GE
Logo GE
Description 256-Word by 4-Bit LSI Static Random-Access Memory
Datasheet CDP1822C DatasheetCDP1822C Datasheet (PDF)

Random-Access Memories (RAMs) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __ CDP1822, CDP1822C 03 A2 AI AD A5 A6 A7 VSS Dr I 001 012 22 2I 20 19 18 17 16 15 9 I. 10 13 " 12 TOP VIEW Voo O. Riw CSi 00 C52 DO. 014 003 DB 002 92CS-29976 RI CDP1822, CDP1822C TERMINAL ASSIGNMENTS 256-Word by 4-Bit LSI Static Random-Access Memory Features: • Low operating current-8 mA at Voo=5 V and cycle time=1 /is • Industry standard pinout • Two Chip-Select inputs-simple memory expansion • Memory retention for sta.

  CDP1822C   CDP1822C







High-Reliability CMOS 256-Word x 4-Bit LSI Static RAM

CDP1822C/3 March 1997 High-Reliability CMOS 256-Word x 4-Bit LSI Static RAM Description The CDP1822C/3 is a 256 word by 4-bit random access memory designed for use in memory systems where high speed, low operating current, and simplicity in use are desirable. The CDP1822 features high speed and excellent noise immunity. It has separate data inputs and outputs and utilizes a single power supply of 4V to 6.5V. Two Chip Select inputs simplify system expansion. An output Disable control provides Wire-OR-capability and is also useful in common Input/Output systems. The Output Disable input allows this RAM to be used in common data Input/Output systems by forcing the output into a high impedance state during a write operation independent of the Chip Select input condition. The output assumes a high impedance state when the Output Disable is at high level or when the chip is deselected by CS1 and/or CS2. The high noise immunity of the CMOS technology is preserved in this design. For TTL interfacing at 5V operation, excellent system noise margin is preserved by using an external pull-up resistor at each input. Features • For Applications in Aerospace, Military, and Critical Industrial Equipment • Interfaces Directly with CDP1802 Microprocessor • Very Low Operating Current - At VDD = 5V and Cycle Time = 1µs . . . . . . 4mA (Typ) • Static CMOS Silicon-On-Sapphire Circuitry - CD4000 Series Compatible • Industry Standard Pinout • Two Chip Select Inputs - Simple Memory Expansion • Memor.


2005-03-23 : 2N2857CSM    2N2880    2N2891    2N2894    2N2894    2N2894    2N2894A    2N2894ACSM    2N2894CSM    2N2894DCSM   


@ 2014 :: Datasheetspdf.com ::
Semiconductors datasheet search & download site (Privacy Policy & Contact)