CDP1882

CDP1881C, CDP1882, CDP1882C March 1997 CMOS 6-Bit Latch and Decoder Memory Interfaces Description The CDP1881C, CDP1882 and CDP1882C are CMOS 6-bit memory latch and decoder circuits intended for use in CDP1800 series microprocessor systems. They can interface directly with the multiplexed address bus of this system at maximum clock frequency, and up to four 4K x 8-bit memories to provide a 16K byte memory system. With four 2K x 8-bit memories an 8K byte system can be decoded. The devices are also compatible with non-multiplexed address bus microprocessors. By connecting the clock input to VDD, the latches are in the data-following mode and the decoded outputs can be used in general purpose memorysystem applications. The CDP1881C, CDP1882 and CDP1882C are intended for use with 2K or 4K byte RAMs and are identical except that in the CDP1882 MWR and MRD are excluded. The CDP1882 is functionally identical to the CDP1882C. It differs in that the CDP1882 has recommended operating voltage range of 4V to 10.5V and the C version has a recommended operating voltage range of 4V to 6.5V. The CDP1881C, CDP1882 and CDP1882C are supplied in 20 lead and 18 lead packages, respectively. The CDP1881C is supplied only in a dual-in-line plastic package (E suffix). The CDP1882 is supplied in dual-in-line, hermetic side-brazed ceramic (D suffix) and in plastic (E suffix) packages. Features Performs Memory Address Latch and Decoder Functions Multiplexed or Non-Multiplexed Decodes Up to 16K Bytes ...