Converter. CS5360 Datasheet

CS5360 Datasheet PDF

Part CS5360
Description 24-Bit Stereo A/D Converter
Feature CS5360; CS5360 24-Bit Stereo A/D Converter for Digital Audio Features l 24 Bit Conversion l 105 dB Dynamic.
Manufacture Cirrus Logic
Datasheet
Download CS5360 Datasheet




CS5360
CS5360
24-Bit Stereo A/D Converter for Digital Audio
Features
l 24 Bit Conversion
l 105 dB Dynamic Range
l -95 dB THD+N
l 128X Oversampling
l Fully Differential Inputs
l Linear Phase Digital Anti-Alias Filtering
– 21.7 kHz passband (Fs = 48kHz)
– 85 dB stop band attenuation
– 0.0025 dB pass band ripple
l High Pass Filter - DC Offset Removal
l Peak Signal Level Detector
– High Resolution and Bar Graph Modes
l Pin Compatible with CS5334 and CS5335
I
Description
The CS5360 is a 2-channel, single +5 V supply, 24-bit
analog-to-digital converter for digital audio systems. The
CS5360 performs sampling, analog-to-digital conversion
and anti-alias filtering, generating 24-bit values for both
left and right inputs in serial form. The output word rate
can be up to 50 kHz per channel.
The CS5360 uses 4th-order, delta-sigma modulation
with 128X oversampling followed by digital filtering and
decimation, which removes the need for an external anti-
alias filter. This ADC uses a differential architecture
which provides excellent noise rejection.
The CS5360 has a filter passband to 21.7 kHz. The filter
has linear phase, 0.0025 dB passband ripple, and
>85 dB stopband rejection. An on-chip high pass filter is
also included to remove DC offsets.
ORDERING INFORMATION
CS5360-KS -10° to 70°C
CS5360-BS -40° to 85°C
20-pin Plastic SSOP
20-pin Plastic SSOP
15
CMOUT
VA+ VD+
36
Voltage Reference
RST MCLK
18 7
16
AINL-
17
AINL+
S/H
+
-
14
AINR-
13
AINR+
S/H
+
-
LP Filter
DAC
+
-
Comparator
LP Filter
DAC
+
-
Comparator
OVFL FRAME SCLK LRCK
2 10
8 12
Serial Output Interface
9
20
19
SDATA
DIF0
DIF1
Digital
Decimation
Filter
High
Pass
Filter
Digital
Decimation
Filter
High
Pass
Filter
4
AGND
5
DGND
11
PU
1
HP DEFEAT
Preliminary Product Information
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com
Copyright © Cirrus Logic, Inc. 1999
(All Rights Reserved)
OCT ‘99
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CS5360
CS5360
TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 3
ANALOG CHARACTERISTICS ................................................................................................ 3
DIGITAL FILTER CHARACTERISTICS.................................................................................... 4
DIGITAL CHARACTERISTICS ................................................................................................. 4
ABSOLUTE MAXIMUM RATINGS ........................................................................................... 4
SWITCHING CHARACTERISTICS .......................................................................................... 5
2. SYSTEM DESIGN ..................................................................................................................... 8
2.1 Master Clock ...................................................................................................................... 8
3. SERIAL DATA INTERFACE ..................................................................................................... 8
3.1 Serial Data ......................................................................................................................... 8
3.2 Serial Clock ........................................................................................................................ 8
3.3 Left / Right Clock .............................................................................................................. 10
3.4 Master Mode .................................................................................................................... 10
3.5 Slave Mode ...................................................................................................................... 10
3.6 Analog Connections ......................................................................................................... 10
3.7 High Pass Filter ................................................................................................................ 10
4. INPUT LEVEL MONITORING ................................................................................................. 11
4.1 High Resolution Mode ...................................................................................................... 11
4.2 Bar Graph Mode .............................................................................................................. 12
4.3 Overflow ........................................................................................................................... 12
4.4 Initialization ...................................................................................................................... 12
4.5 Initialization with High Pass Filter Enabled ...................................................................... 12
4.6 Initialization and Internal Calibration with High Pass Filter Disabled ............................... 12
4.7 Power-Down .................................................................................................................... 13
4.8 Grounding and Power Supply Decoupling ....................................................................... 13
4.9 Digital Filter ...................................................................................................................... 13
5. PIN DESCRIPTIONS .............................................................................................................. 15
6. PARAMETER DEFINITIONS .................................................................................................. 18
7. PACKAGE DIMENSIONS ....................................................................................................... 19
LIST OF FIGURES
Figure 1. SCLK to SDATA & LRCK - MASTER Mode Format 0 and 1 ........................................... 6
Figure 3. SCLK to LRCK & SDATA - SLAVE Mode Format 0 & 1 .................................................. 6
Figure 2. SCLK to SDATA & LRCK - MASTER Mode Format 2 ..................................................... 6
Figure 4. SCLK to LRCK & SDATA - SLAVE Mode Format 2......................................................... 6
Figure 5. SCLK to Frame Delay ...................................................................................................... 6
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:
http://www.cirrus.com/corporate/contacts/
Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product infor-
mation describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information
contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of
any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights
of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of
this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or
otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no
part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical,
photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication maybe used as a basis for manufacture
or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing
in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trade-
marks and service marks can be found at http://www.cirrus.com.
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CS5360
CS5360
Figure 6. Typical Connection Diagram............................................................................................ 7
Figure 7. Data Block and Frame ..................................................................................................... 8
Figure 8. Serial Data Format 0........................................................................................................ 9
Figure 9. Serial Data Format 1........................................................................................................ 9
Figure 10. Serial Data Format 2...................................................................................................... 9
Figure 11. Full Scale Input Levels................................................................................................. 10
Figure 12. CS5360 Digital Filter Passband Ripple........................................................................ 14
Figure 13. CS5360 Digital Filter Transition Band.......................................................................... 14
Figure 14. CS5360 Digital Filter Stopband Rejection.................................................................... 14
Figure 15. CS5360 Digital Filter Transition Band.......................................................................... 14
LIST OF TABLES
Table 1. Common Clock Frequencies............................................................................................. 9
Table 2. Digital Input Formats ......................................................................................................... 9
Table 3. Peak Signal Level Bits - High Resolution Mode.............................................................. 12
Table 4. P7 to P0 - Peak Signal Level Bits -Bar Graph Mode....................................................... 13
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