CTL0035NS-R3

CTL0035NS-R3 N-Channel Enhancement MOSFET Features Drain-Source Breakdown Voltage VDSS 50 V Drain-Source On-Resistance RDS(ON) 1.3Ω, at VGS= 10V, ID= 0.2A RDS(ON) 1.4Ω, at VGS= 5V, ID= 0.2A RDS(ON) 1.6Ω, at VGS= 2.75V, ID= 0.2A ℃ Continuous Drain Current at TA=25 ID = 0.3A Advanced high cell density Trench Technology RoHS Compliance & Halogen Free Applications DC/DC Converter Load Switch LCD Display inverter Power Management Description The CTL0035NS-R3 is the N-Channel logic enhancement mode power field effect transistors are produced using high cell density, DMOS trench technology. This high density process is especially tailored to minimize on-state resistance. Package Outline Schematic Drain Drain Gate Source Gate Source CT Micro Proprietary & Confidential Page 1 Rev 2 Jun, 2015 CTL0035NS-R3 N-Channel Enhancement MOSFET Absolute Maximum Rating at 25oC Symbol Parameters VDS Drain-Source Voltage VGS Gate-Source Voltage ℃ID Continuous Drain Current @TA=25 IDM Pulsed Drain Current ℃PD Total Power Dissipation @TA=25 TSTG Storage Temperature Range TJ Operating Junction Temperature Range Thermal Characteristics Symbol Parameters RӨJA4 Thermal Resistance Junction-Ambient (t=10s) Test Conditions Test Conditions 50 ±20 0.3 1 0.36 -55 to 150 -55 to 150 Min Notes V V A1 A1 W2 °C °C Min Typ Max Units Notes -- 350 -- oC /W 1,4 CT Micro Proprietary & Confidential Page 2 Rev 2 Jun, 2015 CTL0035NS-R3 N-Channel Enhancement MOSFET Electr...